Semiconductor Protective Layer with Apertures for Adhesion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor devices face issues with die peeling due to gaps created by protective layers, which reduce the surface area for adhesive adhesion and allow molding compounds to apply force, leading to adhesive layer peeling.

Innovation Solution

A protective layer is positioned between semiconductor dies, with a periphery that covers the first die's surface and includes apertures for the adhesive layer to fill, ensuring full contact and preventing peeling by eliminating gaps and increasing adhesion surface area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protective layer is provided on the die surface, then the electrical interfaces and metal layers are protected, but the surface area for adhesive adhesion is reduced and gaps are created causing die peeling

Engineering Contradiction:
Improveprotection of electrical interfacesVSAvoidadhesive bond strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The protective layer is configured with a porous structure containing multiple voids that extend through its thickness. These voids allow the adhesive layer to penetrate and form mechanical interlocking bonds, significantly increasing the effective adhesion surface area while maintaining the protective function of the layer

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The adhesive layer is positioned to extend through the voids of the protective layer, creating a nested structure where the adhesive penetrates and bonds to both the protective layer and the die surface beneath, effectively combining multiple bonding surfaces within a single adhesive application

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If a protective layer is positioned between the die and adhesive layer, then the die surface is protected, but gaps are created into which molding compound may flow causing peeling

Engineering Contradiction:
Improveprotection of die surfaceVSAvoidmolding compound infiltration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The porous structure of the protective layer with controlled void distribution allows the adhesive to fill and seal the gaps, preventing molding compound from penetrating into spaces that would cause peeling while maintaining the protective barrier function

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The adhesive layer acts as an intermediary substance that fills the voids in the protective layer, creating a sealed transition zone between the protective layer and the die, thereby preventing harmful molding compound infiltration while maintaining structural integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the occurrence of die peeling by ensuring the adhesive layer adheres fully to the protective layer and the die, enhancing the structural integrity of the semiconductor device.

Implementation Method 1

an adhesive layer having a top planar surface and a bottom planar surface, the adhesive layer positioned between the protective layer and the second semiconductor die

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS20230260949A1Semiconductor Device with Protective Layer
Publication Date: 2023.08.17 SANDISK TECHNOLOGIES LLC
  • US20230260949A1 patent drawing
  • US20230260949A1 patent drawing
  • US20230260949A1 patent drawing

AI summary

A semiconductor device includes a first semiconductor die having a top planar surface and a second semiconductor die having a bottom planar surface and a top planar surface. A protective layer including a bottom planar surface and a top planar surface is positioned between the first semiconductor die and the second semiconductor die. An adhesive layer having a top planar surface and a bottom planar surface is between the protective layer and the second semiconductor die. A periphery of the top planar surface of the first semiconductor die is covered by a periphery of the bottom planar surface of the protective layer after cutting a portion of the protective layer that extended past the periphery of the surface of the first semiconductor die. The protective layer reduces the occurrence of peeling of the second semiconductor die and first semiconductor die coupled to the protective layer.