Semiconductor Protective Layer Layout for Crack-Free High-Voltage Insulation

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Solution Overview

Problem

Semiconductor devices experience thermal deformation and internal stress in the protective layer due to heating and cooling, leading to potential cracks that can compromise the dielectric breakdown strength, especially under high voltage applications.

Innovation Solution

The semiconductor device design features a protective layer with a thinner thickness at the outer peripheral end compared to the electrode layer disposing portion, reducing internal stress and the likelihood of cracks, while maintaining or increasing the thickness of the protective layer to enhance moisture resistance and creepage distance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the protective layer thickness is increased to prevent moisture ingress and enhance creepage distance, then moisture resistance and electrical insulation are improved, but internal stress and crack occurrence are exacerbated

Engineering Contradiction:
Improvemoisture resistanceVSAvoidcrack resistance
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The protective layer is designed with non-uniform thickness, being thicker at the center portion and thinner at the outer peripheral end. This local quality variation allows the center to provide superior moisture resistance and electrical insulation, while the thinner peripheral region reduces internal stress and prevents crack occurrence during thermal cycling.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The thickness parameter of the protective layer is deliberately varied across different regions. The thickness ratio between the center portion and outer peripheral end is controlled within a specific range (1.2-3.0), optimizing the balance between moisture barrier performance and stress resistance.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If the protective layer thickness is uniform throughout, then manufacturing simplicity is maintained, but stress concentration occurs at the outer peripheral end during thermal expansion and contraction

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidinternal stress
Core Design Contradiction:
Ease of manufactureVSStress or pressure

Solution Approach 1:

Rather than maintaining uniform thickness for manufacturing simplicity, the invention introduces controlled local variation in thickness. The gradual transition from thinner peripheral regions to a thicker center portion is achieved through controlled deposition or growth processes, balancing manufacturing feasibility with stress distribution optimization.

Inventive Principle:
Principle #3Local quality

3Strength

If the protective layer is made thinner at the outer peripheral end to reduce internal stress, then crack occurrence is suppressed, but moisture barrier performance may be compromised

Engineering Contradiction:
Improvecrack resistanceVSAvoidmoisture resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The protective layer's thickness is optimized for different functional requirements in different regions. The thinner outer peripheral end prioritizes crack resistance and stress relief, while the thicker center portion maintains effective moisture barrier performance. This spatial differentiation of thickness resolves the apparent contradiction between crack resistance and moisture resistance.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively suppresses the occurrence of cracks in the protective layer, preventing moisture ingress and maintaining high dielectric breakdown strength, even under high voltage conditions, thus ensuring reliable operation of the semiconductor device.

Implementation Method 1

when the semiconductor device is heated or cooled, the protective layer may be thermally deformed by expansion or contraction

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

when the semiconductor device is heated or cooled, the protective layer may be thermally deformed by expansion or contraction

Methodology Applied
Scientific EffectThermal contraction: Thermal Contraction

Data Source

PatentUS12100671B2Semiconductor device
Publication Date: 2024.09.24 MURATA MFG CO LTD
  • US12100671B2 patent drawing
  • US12100671B2 patent drawing
  • US12100671B2 patent drawing

AI summary

A semiconductor device that includes a semiconductor substrate having a first main face and a second main face opposite each other; a dielectric film on a part of the first main face, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in an outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion of the dielectric film; a first electrode layer on the electrode layer disposing portion of the dielectric film; and a protective layer continuously covering a range from an end portion of the first electrode layer to the outer peripheral end of the dielectric film.