Semiconductor Package Protrusion Alignment Hybrid Bonding
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving fine pitches and reliable connections between multiple semiconductor chips, which are essential for compact and high-performance electronic devices.
Innovation Solution
A semiconductor package design that includes a lower semiconductor chip with a protrusion and a cover insulating layer, allowing for the stacking and electrical connection of upper semiconductor chips using bonded pads across insulating layers, enhancing alignment accuracy and reducing package size while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are stacked with increasing number of connecting members, then connection reliability is improved, but pitch size decreases making alignment more difficult
Solution Approach 1:
The patent introduces an intermediary alignment structure consisting of protrusions on the lower chip and corresponding recesses on upper chips. This mechanical alignment feature acts as a mediator that guides and constrains the relative positioning of chips during assembly, ensuring accurate alignment of the fine-pitch connecting members without requiring high-precision alignment equipment.
Solution Approach 2:
The alignment protrusions and recesses are pre-formed on the chips before the final assembly process. This preliminary structuring of alignment features allows the chips to self-align during stacking, reducing the alignment complexity and improving manufacturing precision for packages with multiple connecting members.
2Area of stationary object
If the horizontal area of upper semiconductor chip is reduced to be superimposed on protrusion, then package size is reduced, but alignment accuracy must be maintained
Solution Approach 1:
The patent employs asymmetric design where the upper semiconductor chip has a smaller horizontal area that is strategically positioned to superimpose on the protrusion of the lower chip. This asymmetric stacking arrangement reduces the overall package footprint while the protrusion-recess alignment mechanism ensures that alignment accuracy is maintained despite the size reduction.
3Quantity of substance
If fine pitches are used for connecting members, then connection density is increased, but alignment difficulty increases
Solution Approach 1:
The protrusion-recess alignment structure serves as a mechanical intermediary that compensates for the increased alignment difficulty associated with fine-pitch connecting members. By providing a coarse alignment mechanism at the chip level, the system enables precise positioning of fine-pitch interconnects without requiring equally fine alignment precision in the assembly process.
Data Source
AI summary
A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.