3D Semiconductor Device With Protruding Sidewalls
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of fine pattern formation, necessitating the development of three-dimensional semiconductor devices with improved reliability and cost-effectiveness.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure of alternately stacked insulating layers and electrodes, horizontal semiconductor patterns, and vertical semiconductor patterns connected to the substrate, featuring a unique sidewall profile with protrusions to enhance integration density and prevent shorts between common source plugs and horizontal semiconductor patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern formation techniques are used to increase integration density in 2D semiconductor devices, then integration density is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical structures. The stack structure with alternating insulating layers and electrodes, combined with vertical semiconductor patterns penetrating through the stack, enables integration density improvement by utilizing the vertical dimension rather than relying solely on fine pattern formation in the horizontal plane.
Solution Approach 2:
The semiconductor device is segmented into distinct functional regions: a stack structure with alternating insulating layers and electrodes, horizontal semiconductor patterns, and vertical semiconductor patterns. This segmentation allows each component to be optimized independently while achieving high integration density through their coordinated three-dimensional arrangement.
2Quantity of substance
If conventional planar structures are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The invention employs a three-dimensional architecture where vertical semiconductor patterns penetrate through horizontally stacked insulating and electrode layers. This vertical integration approach achieves high integration density without requiring extremely fine horizontal patterning, thereby maintaining relative manufacturing simplicity while dramatically increasing device capacity.
Solution Approach 2:
The structure features nested arrangements where vertical semiconductor patterns are embedded within and penetrate through the horizontally stacked insulating layers and electrodes. This nesting configuration maximizes space utilization and integration density while maintaining a manufacturable hierarchical structure.
3Quantity of substance
If horizontal semiconductor patterns are placed close to common source plugs, then integration density increases, but electrical shorts may occur
Solution Approach 1:
The horizontal semiconductor pattern incorporates localized protrusions at specific regions where it approaches the common source plug. These protrusions create a controlled geometric configuration that maintains electrical isolation while minimizing spacing requirements, thereby achieving high integration density without compromising electrical reliability.
Solution Approach 2:
The protrusions on the horizontal semiconductor pattern create curved or non-linear geometric features that optimize the spatial relationship with the common source plug. This curved geometry allows the pattern to approach the plug more closely while maintaining adequate electrical clearance, improving integration density without causing shorts.
Data Source
AI summary
A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.