Semiconductor FinFET Pseudofin Support Structure

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Solution Overview

Problem

In semiconductor manufacturing, the reduction in feature size of integrated circuits leads to short-channel effects in MOSFETs, where the gate structure's control over channels becomes weaker, causing subthreshold leakage and making it difficult to pinch off the channel, especially with the transition from planar MOSFETs to three-dimensional transistors like FinFETs.

Innovation Solution

A semiconductor structure and forming method that involves etching a base to form independent fin portions and pseudofin portions, with the pseudofin portions acting as a support between the fin portions to improve the uniformity of isolating layers and reduce the likelihood of fin portions being bent or inclined, and removing the pseudofin portions to enhance height uniformity and prevent substrate exposure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the feature size of integrated circuits is reduced, then the integration density is improved, but the gate structure's control over channels deteriorates, causing short-channel effects and subthreshold leakage

Engineering Contradiction:
Improveintegration densityVSAvoidgate control capability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar MOSFETs to FinFETs by introducing a three-dimensional fin structure. The gate structure wraps around the fin from two sides, creating a vertical control geometry that enhances gate control capability while maintaining high integration density through reduced feature sizes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple spaced filling layers are etched to form pseudofin portions, then the uniformity of isolating layers is improved, but the device complexity increases

Engineering Contradiction:
Improveuniformity of isolating layersVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent forms pseudofin portions from filling layers before forming the isolating layers. These pseudofin portions serve as preliminary support structures that maintain uniform spacing and prevent bending or inclination of the fin portions during subsequent processing steps, ensuring uniform isolating layer formation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pseudofin portions formed from filling layers act as intermediary support structures between the fin portions. They provide mechanical support during the isolating layer formation process, preventing fin portion deformation and ensuring uniform isolating layer thickness

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11075287B2Semiconductor structure and forming method thereof
Publication Date: 2021.07.27 SEMICON MFG INT (SHANGHAI) CORP
  • US11075287B2 patent drawing
  • US11075287B2 patent drawing
  • US11075287B2 patent drawing

AI summary

The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. In one form, a method for forming a semiconductor structure includes: providing a base; forming multiple spaced filling layers in the base; etching the base to form multiple independent fin portions; and etching the filling layers to form multiple independent pseudofin portions. In one form a semiconductor structure of the present disclosure includes: a substrate, multiple independent fin portions and multiple independent pseudofin portions, wherein the substrate includes device areas, and isolating areas located between the device areas; the multiple independent fin portions are located on the substrate in the device areas and are the same with the substrate in material; and the multiple independent pseudofin portions are located on the substrate in the isolating areas and are different from the substrate in material.