Semiconductor Device QLC PLC Disturb Resistance
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges in improving operation reliability due to susceptibility to program disturb and VPASS disturb, especially when both quad-level cells (QLC) and penta-level cells (PLC) coexist, leading to increased disturb resistance requirements.
Innovation Solution
The semiconductor device alternately arranges QLC and PLC memory cells in the Z direction, with a peripheral circuit applying a high program pass voltage to non-selected memory cells with fewer bits, thereby alleviating electric field stress and improving disturb resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If both QLC and PLC memory cells are stacked in the Z direction, then storage capacity is improved, but disturb resistance deteriorates due to increased susceptibility to program and VPASS disturbs
Solution Approach 1:
The memory cell stack is segmented into different cell types (QLC and PLC) with different bit capacities. By dividing the stack into segments with different characteristics, the patent can apply different voltages to different segments during programming operations, thereby managing disturb effects more effectively while maintaining high storage capacity.
Solution Approach 2:
Different voltage levels are applied to different local regions (QLC vs PLC cells) during programming operations. The patent applies higher program pass voltages to QLC cells and lower voltages to PLC cells, creating local quality differences in voltage application that reduce disturb effects on non-selected cells while maintaining programming efficiency.
2Speed
If high program pass voltage is applied to all non-selected memory cells, then programming speed is improved, but disturb resistance deteriorates due to increased susceptibility to program and VPASS disturbs in QLC and PLC cells
Solution Approach 1:
The patent applies different program pass voltages to different cell types based on their local characteristics. QLC cells receive higher program pass voltages (e.g., 10V-20V) while PLC cells receive lower voltages (e.g., 5V-10V). This local differentiation allows fast programming where needed while protecting against disturbs in sensitive cells.
Solution Approach 2:
The programming voltage levels are dynamically adjusted based on the cell type being programmed. The system can switch between different voltage levels depending on whether QLC or PLC cells are being programmed, and can also adjust voltages based on the programming state and requirements of different cells in the stack.
Data Source
AI summary
A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.