Semiconductor Patterning Using Self-Aligned Quadruple Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink, the spacing between elements (pitch) approaches and surpasses the limits of traditional photolithography equipment, making it challenging to manufacture devices with smaller dimensions using existing processing techniques.
Innovation Solution
A self-aligned quadruple patterning process is employed to pattern lines on a substrate, allowing for features with a pitch one quarter of the minimum photolithographic pitch by forming multiple layers and using a tri-layer photoresist to transfer patterns to a target layer, which simplifies the cutting process and reduces defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography equipment is used, then manufacturing process is simple, but minimum pitch is limited and cannot achieve smaller dimensions
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps (mandrel formation, spacer deposition, mandrel removal, repeat cycles) to achieve pitch multiplication. Each step creates a portion of the final pattern, with the number of features being the product of features per cycle and number of cycles, thereby overcoming single-step photolithography limits.
Solution Approach 2:
The patent transitions from planar 2D patterning to 3D multi-layer processing by forming spacers on sidewalls of mandrels, depositing additional mandrels in inter-spacer regions, and using vertical spacer layers. This dimensional expansion enables pitch multiplication beyond the limits of traditional 2D photolithography.
2Manufacturing precision
If multiple patterning steps are performed to reduce pitch, then smaller dimensions are achieved, but process complexity and defect rates increase
Solution Approach 1:
The patent performs preliminary spacer formation and mandrel preparation in advance of final pattern transfer. By pre-forming spacers with controlled thickness and positioning, and preparing mandrels with appropriate dimensions before the patterning cycle, the process reduces variability and defect formation during subsequent steps.
Solution Approach 2:
The self-aligned nature of the process allows previously formed structures (spacers, mandrels) to automatically serve as alignment references for subsequent deposition and patterning steps. This self-alignment mechanism eliminates the need for additional alignment operations and reduces misalignment defects.
3Manufacturing precision
If intermediate cutting operations are performed during patterning, then pattern accuracy is maintained, but process complexity and defect opportunities increase
Solution Approach 1:
The patent combines multiple patterning operations into unified process cycles where mandrels, spacers, and etch masks are formed and processed together in coordinated sequences. By merging these operations rather than performing them as separate cutting steps, the process maintains pattern accuracy while reducing overall complexity.
Data Source
AI summary
A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further includes forming a first spacer layer on sidewalls and tops of the first mandrels. The method further includes removing horizontal portions of the first spacer layer, with remaining vertical portions of the first spacer layer forming first spacers. The method further includes, after removing the horizontal portions of the first spacer layer, depositing a reverse material between the first spacers. The method further includes patterning the first mask layer using the first spacers and the reverse material in combination as a first etching mask.