Semiconductor Quantum Dot Rows With an Intermediary Qubit Bus
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scaling up two-dimensional qubit arrays in semiconductor quantum dot-based systems is challenging due to the difficulty in individually accessing each qubit, particularly in central parts of large arrays, caused by the small physical size of qubits and the need for wide frequency-range analog voltage signals, which exacerbates wiring fanout and crosstalk effects.
Innovation Solution
A quantum device architecture that remaps a conventional 2D qubit array into a pair of linear 1D arrays and an intermediate qubit bus, allowing qubits to be transferred and shuttled between rows of quantum dots and qubit sites, enabling interactions without requiring long-range qubit coupling or resonators, and utilizing CMOS technology for scalable fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional 2D qubit array is used to achieve high qubit density, then the number of qubits can be increased, but individual access to qubits becomes difficult due to wiring fanout and crosstalk effects
Solution Approach 1:
The patent segments the 2D qubit array into multiple 1D rows of quantum dots that are coupled to a shared qubit bus. This segmentation allows qubits to be individually accessed through the bus without requiring direct wiring to each qubit, thereby maintaining ease of operation while increasing qubit density. The bus acts as an intermediary that simplifies the control architecture.
Solution Approach 2:
The qubit bus serves as an intermediary component between the control electronics and the quantum dots. Instead of wiring directly to each qubit, control signals are routed through the bus, which then couples to individual quantum dots. This intermediary structure reduces wiring fanout and crosstalk while enabling individual qubit access in large-scale arrays.
2Area of moving object
If the physical size of qubits is reduced to increase integration density, then more qubits can be integrated, but individual access becomes more difficult due to small size and crosstalk
Solution Approach 1:
The qubit bus acts as an intermediary that enables access to small-scale quantum dots without requiring direct proximity wiring. The bus provides a standardized interface that decouples the physical size of qubits from the complexity of access mechanisms, allowing small qubits to be individually controlled through the bus architecture.
Solution Approach 2:
The qubit bus provides a universal access mechanism that works for all quantum dots in the array regardless of their physical size or position. This multi-functional bus structure enables individual access to both small and large qubits using the same control protocol, simplifying operation across different scaling regimes.
3Ease of operation
If wide frequency-range analog voltage signals are applied to each qubit for operations, then qubit control is achieved, but wiring fanout and crosstalk effects are exacerbated
Solution Approach 1:
The qubit bus serves as an intermediary that consolidates the control signals for multiple quantum dots into a single communication channel. Instead of applying wide frequency-range voltage signals directly to each qubit through separate wires, the bus mediates signal distribution, thereby reducing wiring fanout and crosstalk while maintaining full qubit control capability.
Solution Approach 2:
The patent merges the control pathways for multiple quantum dots into a single qubit bus structure. By combining what would otherwise be multiple separate wiring channels into one shared bus, the system reduces wiring fanout and crosstalk effects while preserving the ability to independently control each qubit through frequency-selective addressing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture facilitates easier scalability of qubit arrays, reduces the number of horizontal shuttles needed, minimizes cross-talk, and allows for a simple and regular layout, while maintaining high fidelity operations and compatibility with standard silicon manufacturing.
Implementation Method 1
a first set of control gates configured to define a first row of electrostatically confined quantum dots and a second set of control gates configured to define a second row of electrostatically confined quantum dots
Implementation Method 2
each quantum dot of the first and second rows is configured to be tunnel coupled to a qubit site of the row of qubit sites so as to allow a spin qubit to be transferred between the quantum dot and the qubit bus
Implementation Method 3
the qubit sites are configured to be sequentially tunnel coupled to each other so as to allow a spin qubit transferred to the qubit bus to be shuttled between the qubit sites of the row of qubit sites
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
In an aspect there is provided a quantum device comprising: a semiconductor substrate; a first set of control gates configured to define a first row of electrostatically confined quantum dots and a second set of control gates configured to define a second row of electrostatically confined quantum dots, wherein each quantum dot is suitable for holding a spin qubit, and wherein the first and second rows extend in parallel in a longitudinal direction along the semiconductor substrate; and a qubit bus configured to define a row of qubit sites extending along the semiconductor substrate in parallel to and between the first and second rows of quantum dots, wherein each quantum dot of the first and second rows is configured to be tunnel coupled to a qubit site of the row of qubit sites so as to allow a spin qubit to be transferred between the quantum dot and the qubit bus, and wherein the qubit sites are configured to be sequentially tunnel coupled to each other so as to allow a spin qubit transferred to the qubit bus to be shuttled between the qubit sites of the row of qubit sites.