Semiconductor Package RDL Layout for EMI Shielding and Routing Density
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Solution Overview
Problem
The increasing bandwidth of semiconductor dies requires more ground lines and planes for interference suppression, limiting the routing area of the redistribution layer (RDL) or interposer, which restricts the integration density and efficiency of semiconductor packages.
Innovation Solution
A semiconductor package design featuring a redistribution structure with multiple routing layers, including signal lines and ground lines/planes, where the signal lines are routed from a central region to a peripheral region, allowing for increased routing area and reduced susceptibility to stress, and an interposer with similar interconnection structures, effectively managing signal and ground line placement to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If more ground lines and ground planes are added to suppress interference between adjacent signal lines, then electromagnetic interference suppression is improved, but routing area is reduced
Solution Approach 1:
The patent utilizes multiple routing layers stacked vertically to provide three-dimensional routing space. By distributing signal lines and ground planes across different layers (first routing layer, second routing layer, third routing layer), the design achieves effective electromagnetic shielding without consuming excessive planar routing area, thus resolving the contradiction between interference suppression and routing area availability
2Area of stationary object
If signal lines are routed through the central region, then routing area is increased, but stress susceptibility increases
Solution Approach 1:
The patent implements differentiated routing strategies for different types of lines based on their functional requirements. Signal lines are routed through the central region to maximize routing area, while ground lines are specifically routed through the peripheral region where mechanical stress is lower. This local optimization of routing paths addresses both the need for increased routing area and reduced stress susceptibility
3Area of stationary object
If more routing layers are added to increase routing area, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent divides the routing structure into multiple functional layers with distinct roles: the first routing layer handles signal lines, the second routing layer provides ground planes for shielding, and the third routing layer handles additional signal routing. This segmentation allows each layer to be optimized independently, achieving high integration density while maintaining manageable complexity through clear functional separation
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.