Semiconductor Package RDL Stacking for Miniaturization
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in achieving high-capacity and miniaturization due to increased I/O pads on memory chips, making it difficult to stack memory chips on logic chips with limited size without using costly interposers or printed circuit boards, which hinders signal transfer rate and performance.
Innovation Solution
A semiconductor package and manufacturing method that utilizes redistribution layers (RDLs) to directly connect devices without a high-priced interposer or printed circuit board, reducing package thickness by designing input/output pads through RDLs, and using encapsulant materials to protect and position bond pads and conductive bumps for efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chip capacity is increased by integrating more cells, then memory capacity is improved, but the number of I/O pads increases making the chip bulky
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking architecture. Multiple memory chips are stacked vertically on a substrate, utilizing the vertical dimension to increase memory capacity without expanding the horizontal chip area. This allows high-capacity memory modules to be formed within a compact footprint.
2Quantity of substance
If memory chip is stacked on logic chip to provide high-capacity module, then memory capacity is improved, but package thickness increases and signal transfer rate deteriorates
Solution Approach 1:
The patent introduces a substrate as an intermediary component that electrically connects multiple memory chips in a stacked configuration. The substrate provides signal routing pathways that reduce the effective signal transmission distance compared to direct chip-to-chip connections, thereby maintaining signal transfer rate while enabling vertical stacking for increased capacity.
3Adaptability or versatility
If conventional stacking method is used with limited substrate size, then device integration is achieved, but I/O pad layout becomes difficult and signal transfer rate is limited
Solution Approach 1:
The patent segments the I/O pad layout into multiple layers corresponding to different stacked memory chips. Each memory chip's I/O pads are independently arranged and connected through the substrate, allowing flexible pad placement and routing. This segmentation enables effective I/O pad layout management in three-dimensional stacked architectures.
Data Source
AI summary
A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.