Semiconductor RDL Test Pad Layout for Early Defect Detection
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Solution Overview
Problem
The complexity of miniaturized semiconductor device manufacturing leads to issues such as poor electrical interconnection and delamination, resulting in high yield loss, as defects are difficult to identify before the completion of the semiconductor structure.
Innovation Solution
Incorporation of a dummy conductive member during manufacturing allows for electrical testing of die and interconnections, enabling the identification of failures and defects at an earlier stage, thereby minimizing material wastage and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If miniaturized scale manufacturing is implemented, then cost is reduced and functionality is increased, but manufacturing complexity increases and yield loss increases
Solution Approach 1:
The patent introduces dummy conductive members during the manufacturing process that enable preliminary electrical testing of interconnections before the semiconductor device is complete. This preliminary action allows defects to be detected early in the manufacturing process, preventing wasted effort on defective devices and improving overall yield despite the complexity of miniaturized manufacturing
2Length of moving object
If miniaturized scale manufacturing is implemented, then device size is reduced, but defect detection capability deteriorates
Solution Approach 1:
The patent introduces dummy conductive members as intermediary elements that facilitate electrical testing of interconnections. These dummy members serve as accessible test points that allow measurement and detection of electrical defects without requiring direct access to the miniaturized internal interconnections, thereby overcoming the difficulty of detecting defects in small-scale devices
3Adaptability or versatility
If complex manufacturing operations are performed, then device functionality is enhanced, but electrical interconnection quality deteriorates
Solution Approach 1:
The patent implements a feedback mechanism by incorporating dummy conductive members that enable electrical testing during manufacturing. This feedback allows real-time monitoring of interconnection quality, enabling corrective actions to be taken if defects are detected, thereby maintaining high electrical interconnection quality despite the complexity of manufacturing operations
Data Source
AI summary
A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.