Semiconductor Device with Automatic Read-Write Scheduling
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Solution Overview
Problem
Conventional NOR flash memory devices experience a significant delay in write operations and are unable to perform random access read operations efficiently due to the need to suspend write operations when a read operation is initiated, resulting in inferior random access characteristics.
Innovation Solution
A semiconductor device with a memory cell array comprising a first and second memory block, a control signal generation circuit that compares write and read addresses to generate control signals, and a data write block that suspends write operations until read operations are completed, allowing for simultaneous or prioritized read operations without requiring external suspend commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a read operation is performed while a write operation is being performed in conventional NOR flash memory, then the read operation can be executed, but the write operation must be suspended resulting in increased access time and degraded random access characteristics
Solution Approach 1:
The memory device is divided into multiple independent memory blocks (first memory block and second memory block) that can operate simultaneously. The write operation is performed on the first memory block while the read operation is performed on the second memory block, allowing parallel execution without suspension and eliminating recover time.
Solution Approach 2:
The control signal generation circuit dynamically determines operation timing based on address comparison results. When addresses are the same, the write operation is suspended; when addresses are different, operations proceed in parallel. This dynamic control optimizes access time based on real-time conditions.
2Ease of operation
If a read operation is initiated during a write operation in conventional NOR flash memory, then the read operation can be performed, but an external suspend command is required resulting in increased device complexity and reduced ease of operation
Solution Approach 1:
The control signal generation circuit automatically generates the necessary control signals by comparing write and read addresses internally. The system self-determines whether to suspend or proceed with operations based on address matching, eliminating the need for external suspend commands and simplifying the interface.
Solution Approach 2:
The control signal generation circuit uses feedback from address comparison results to automatically adjust operation timing. The comparison output directly controls the timing signal generation, creating a closed-loop system that autonomously manages write suspension without external intervention.
3Productivity
If conventional NOR flash memory performs write operations, then data can be written to memory blocks, but random access read characteristics are inferior due to the need to suspend write operations
Solution Approach 1:
By segmenting the memory into multiple independent blocks with separate write and read paths, the device enables true random access reads during write operations. The first memory block handles writes while the second memory block handles reads, ensuring both operations complete reliably without interference.
Data Source
AI summary
A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.