Semiconductor Recess Formation via Amorphous Etching
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Solution Overview
Problem
Current semiconductor device fabrication methods fail to achieve high reliability and increased operation speed while maintaining complexity and integration density, which are essential for modern electronic devices with low power consumption and multiple functions.
Innovation Solution
The method involves forming a semiconductor device by creating a gate pattern on a substrate, injecting amorphization elements to form amorphous portions, and etching these portions to create recess regions with specific crystal plane orientations, followed by growing epitaxial patterns in these recesses, which enhances the semiconductor device's performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used, then manufacturing process is simple, but reliability and operation speed cannot be improved
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming gate pattern, forming spacers, injecting amorphization elements, etching to create recess regions with specific crystal planes, and forming source/drain patterns. Each step creates a more complex structure that contributes to the final reliability improvement
Solution Approach 2:
The method creates recess regions with specific crystal plane orientations ({110} side surfaces, {100} bottom surface) in localized areas adjacent to the gate pattern. This local structural optimization improves carrier mobility and device reliability without requiring complete restructuring of the entire semiconductor device
2Speed
If conventional fabrication methods are used, then manufacturing process is fast, but operation speed of device is limited
Solution Approach 1:
The method changes the crystal plane orientation parameters of the semiconductor structure by creating recess regions with specific orientations ({110} side surfaces, {100} bottom surface). This parameter change in crystal structure improves carrier mobility and thus operation speed
Solution Approach 2:
The invention introduces vertical dimensionality by forming recess regions that extend into the substrate with specific crystal plane orientations. The multi-faceted recess structure with different crystal planes at different depths and angles creates new pathways for charge carrier movement, enhancing operation speed
3Reliability
If recess regions are formed with larger volume, then electrical characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
Amorphization elements are injected as an intermediary step before etching. These elements modify the local material properties to enable selective etching that automatically forms the desired recess shape with correct crystal plane orientations, reducing the need for high-precision direct etching
Solution Approach 2:
Spacers are formed on the gate pattern sidewalls before the recess formation process. These spacers serve as preliminary structures that define the lateral boundaries of the recess regions, ensuring precise positioning and shape control during subsequent etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the semiconductor device's reliability and operation speed by increasing the volume of recess regions and controlling the crystal plane orientations, leading to enhanced electrical characteristics and mobility of charge carriers.
Implementation Method 1
injecting amorphization elements into the active pattern to form amorphous portions in the active pattern
Implementation Method 2
injecting amorphization elements into the active pattern to form amorphous portions
Implementation Method 3
forming epitaxial patterns in the recess regions
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., <111> and any other direction) of the semiconductor substrate.