Semiconductor Recess Depth Uniformity via Localized Coating Thickness
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Solution Overview
Problem
As semiconductor devices, such as MOS-FETs, are scaled down, their operational properties deteriorate due to size reduction, necessitating improved methods for forming recesses and epitaxial source/drain regions to maintain performance.
Innovation Solution
A method involving a substrate with distinct regions, where different active patterns and gate structures are formed with varying spacings and thicknesses, followed by a coating layer and a recess process to create uniform recesses for epitaxial source/drain growth, allowing for controlled epitaxial layer formation and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If MOS-FETs are scaled down to reduce device size, then device miniaturization is achieved, but operational properties deteriorate
Solution Approach 1:
The patent applies local quality by forming recesses with different depths in different regions of the semiconductor device. Specifically, first recesses are formed in first regions and second recesses are formed in second regions, allowing each region to have optimized characteristics for its specific function while maintaining overall device miniaturization
Solution Approach 2:
The patent segments the semiconductor device into multiple regions with different structures. By dividing the device into first regions and second regions with differently sized and positioned recesses, it enables localized optimization of operational properties while maintaining scaled-down dimensions
2Ease of manufacture
If uniform coating layer thickness is used across different regions, then manufacturing simplicity is maintained, but recess depth uniformity deteriorates
Solution Approach 1:
The patent implements local quality by forming coating layers with different thicknesses in different regions. The first coating layer has a first thickness in first regions and a second thickness in second regions, which compensates for topographical variations and enables uniform recess depths after etching
Solution Approach 2:
The patent applies preliminary action by pre-forming coating layers of different thicknesses before the recess etching process. This preliminary thickness variation compensates for subsequent etching differences, ensuring that recesses achieve uniform depths despite starting from different topographical positions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operational properties of scaled-down semiconductor devices by minimizing differences in recess depth and epitaxial growth rates, reducing technical limitations and maintaining high performance.
Implementation Method 1
forming a coating layer to cover the first and second gate structures and the first and second active patterns
Implementation Method 2
performing a recess process to form a first recess in the first active pattern between the first gate structures and a second recess in the second active pattern between the second gate structures
Implementation Method 3
forming a source/drain epitaxial layer in the first and second recesses
Data Source
AI summary
A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.