Semiconductor Package Recess Through Electrode Design
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high capacity, thinness, and miniaturization while maintaining reliability and simplifying the manufacturing process, particularly in direct bonding methods without adhesive films or connection bumps.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with a recess portion, a protective insulating layer, and a through electrode, along with a second chip bonded directly to the first chip's connection pad, using a method that involves forming recess portions in the substrate and insulating layers to reduce the aspect ratio of through electrodes and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If direct bonding technology is used to integrate more components into a package structure, then component integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The substrate is divided into multiple recess portions, each accommodating a through electrode. This segmentation allows independent formation and alignment of multiple bonding interfaces, enabling higher component integration density while maintaining manageable manufacturing complexity through modular processing
Solution Approach 2:
The invention transitions from planar bonding to three-dimensional bonding by forming recess portions that extend into the substrate. This vertical dimensionality change enables stacking of multiple chips in a compact configuration, significantly increasing integration density without proportionally increasing process complexity
2Reliability
If through electrodes extend deep into the substrate to achieve direct bonding, then bonding reliability is improved, but manufacturing difficulty increases due to high aspect ratio
Solution Approach 1:
Insulating layers are applied selectively to specific regions: a first insulating layer lines the recess portions to provide electrical isolation, while a second insulating layer covers the upper surface to protect exposed through electrode portions. This localized insulation approach enables deep through electrodes to be formed with acceptable aspect ratios while maintaining bonding reliability
Solution Approach 2:
Insulating layers serve as intermediary elements between the through electrodes and the bonding interface. These insulating layers facilitate direct bonding by providing proper electrical isolation and surface preparation, enabling reliable bonding without requiring excessively deep through electrodes
3Device complexity
If adhesive films or connection bumps are eliminated for direct bonding, then manufacturing steps are reduced, but bonding interface reliability may deteriorate
Solution Approach 1:
Through electrodes are formed and insulating layers are applied in advance during substrate processing, before the bonding step. This preliminary preparation ensures that the bonding interfaces are properly prepared with appropriate electrical isolation, enabling reliable direct bonding without requiring additional adhesive films or connection bumps during the bonding process itself
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate having a front surface and a rear surface, a first insulating layer on the rear surface, a recess portion extending into the first substrate through the first insulating layer, a protective insulating layer extending along an inner side surface and a bottom surface of the recess portion, a through electrode extending from the front surface through the bottom surface of the recess portion and the protective insulating layer, and a first connection pad contacting the through electrode in the recess portion, and surrounded by the protective insulating layer, the first semiconductor chip having a flat upper surface defined by upper surfaces of the first insulating layer, the protective insulating layer, the first connection pad; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip.