Semiconductor Recess Epitaxial Regions Isolation
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Solution Overview
Problem
The challenge in forming integrated circuit structures lies in the difficulty of creating transistors with different source/drain epitaxial regions of varying sizes without causing unintentional merger, which can lead to electrical shorts and interfere with device functions, especially when transistors serve different purposes like memory and logic operations.
Innovation Solution
A method involving forming a mask to cover one semiconductor region while recessing another, creating cavities of different depths to grow epitaxial regions of specific sizes, ensuring electrical isolation between SRAM and logic transistors by controlling the depth and width of source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial growth is performed without recessing semiconductor regions, then larger source/drain regions can be formed for logic transistors, but unintentional source/drain epitaxial merger occurs between adjacent transistors causing electrical shorts
Solution Approach 1:
The patent introduces a vertical dimension to the problem by recessing semiconductor regions to different depths before epitaxial growth. Logic transistor regions are recessed deeper than memory transistor regions, creating a height difference that prevents lateral epitaxial merger while allowing each region to grow to its required size. This dimensional differentiation resolves the contradiction between forming large source/drain regions and preventing unintended merger.
Solution Approach 2:
Different semiconductor regions are prepared with different local properties - specifically, different recess depths are created for logic versus memory transistors. This local differentiation allows each region to have optimized epitaxial growth conditions appropriate to its function, preventing merger at interfaces while enabling large growth where needed.
2Reliability
If epitaxial growth time and size are limited to prevent merger, then electrical isolation is maintained, but larger source/drain regions cannot be formed in transistors that benefit from them
Solution Approach 1:
The patent performs preliminary recessing of semiconductor regions to different depths before initiating epitaxial growth. By pre-establishing different starting heights, the system enables subsequent epitaxial growth to proceed for the same duration while naturally producing different final sizes - larger in logic regions and smaller in memory regions - thus achieving both merger prevention and adequate growth capability.
3Adaptability or versatility
If different transistor types are formed close together on a device structure, then device functionality is enhanced, but risk of unintentional source/drain epitaxial merger increases
Solution Approach 1:
The patent resolves the proximity issue by utilizing vertical dimension differentiation through selective recessing. Memory transistors maintain higher semiconductor regions while logic transistors have deeper recesses, creating a vertical separation that prevents lateral epitaxial merger even when transistors are placed close together horizontally, thereby enabling enhanced device functionality without merger risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents source/drain epitaxial merger, allowing for the formation of transistors with appropriate size regions, ensuring functional isolation and preventing electrical shorts, thus enhancing the operational reliability of integrated circuits.
Implementation Method 1
forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region, without covering a second semiconductor region on the substrate and a second gate structure on the second semiconductor region
Implementation Method 2
recessing the second semiconductor region from an initial height above the substrate to a reduced height above the substrate
Implementation Method 3
forming a plurality of cavities by etching the first and second semiconductor regions after removing the mask, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region
Implementation Method 4
forming a plurality of epitaxial regions within the plurality of cavities, the plurality of epitaxial regions including a first source/drain region within the first semiconductor region adjacent the first gate structure, and a second source/drain region within the second semiconductor region adjacent the second gate structure
Data Source
AI summary
Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.