Semiconductor Recess Etching Cycles for Vertical Sidewalls
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Solution Overview
Problem
Deep semiconductor etching processes, such as STiGer and Bosch processes, face challenges in achieving verticality and surface roughness control, leading to scalloping issues in recess formation, which complicates the scaling down of semiconductor devices.
Innovation Solution
A cyclic etching process is employed using a passivation gas during the etching stage and without the etchant in the passivation step, with varying passivation gas components and flow rates to adjust sidewall verticality, surface roughness, and mask selectivity, utilizing isotropic and anisotropic radicals like SF6, SiF4, SiCl4, and C4F8 to form and extend recesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If cyclic etching processes (STiGer and Bosch) are used to achieve deep etching with high aspect ratios, then etching depth and aspect ratio are improved, but surface roughness and scalloping increase along sidewalls
Solution Approach 1:
The patent employs a cyclic etching process that alternates between etching steps (using SF6 plasma) and passivation steps (using C4F8 or CF4 plasma). This periodic application of different gases allows the recess to be etched deeper while the sidewalls are periodically passivated to maintain smoothness. The cycle repeats multiple times to achieve the required depth while controlling surface roughness.
Solution Approach 2:
The patent changes process parameters by switching between different gas compositions and flow rates during etching and passivation steps. During etching, SF6 is used with specific flow rates to achieve high etch rates. During passivation, C4F8 or CF4 is introduced with adjusted flow rates to form protective fluorocarbon polymer layers on sidewalls, thereby controlling surface roughness while maintaining etching depth.
2Shape
If passivation gas is applied simultaneously with etchant to reduce isotropy, then sidewall verticality is improved, but process control becomes difficult
Solution Approach 1:
The patent uses periodic cycling between pure etching steps and pure passivation steps rather than simultaneous application. During etching steps, only SF6 is present to provide anisotropic etching with good verticality. During passivation steps, C4F8 or CF4 is introduced to smooth sidewalls. This periodic separation maintains both verticality and process control.
Solution Approach 2:
The patent dynamically adjusts gas flow rates and plasma power levels between etching and passivation modes. The process transitions between different operational states with optimized parameters for each mode, allowing dynamic control of etch rate, sidewall smoothness, and verticality while maintaining ease of operation through automated sequence control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains process control, reduces scalloping, and adjusts critical dimensions of recesses, enabling more precise and vertical etching in semiconductor devices.
Implementation Method 1
forming an inhibitor layer lining an initial portion of the recess based on first radicals
Implementation Method 2
exposing the initial portion of the recess based on ions
Implementation Method 3
extending the initial portion of the recess with a mixture comprising the first radicals and the second radicals
Data Source
AI summary
A method is provided. The method includes etching a substrate to form a recess in the substrate through a plurality of stages. A first one of the plurality of stages forms an inhibitor layer lining an initial portion of the recess based on first etchant radicals. A second one of the plurality of stages exposes the initial portion of the recess based on ions. A third one of the plurality of stages extends the initial portion of the recess based on second etchant radicals.