Semiconductor Recess Masking for Critical Dimension Uniformity
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in controlling critical dimension uniformity as feature sizes decrease, making it hard to maintain production efficiency and lower costs.
Innovation Solution
The method involves forming a mask layer and multiple covering layers with different thicknesses in recesses of varying widths, using anisotropic etching processes to thin and remove these layers, which improves the uniformity of recesses and through holes, ultimately enhancing critical dimension uniformity and facilitating the formation of semiconductor device structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but critical dimension uniformity becomes more difficult to control and fabrication complexity increases
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching operations with different masking layers. The first etching process forms initial recesses, followed by a first masking layer deposition, then a second etching process forms additional recesses, and finally a second masking layer is deposited. This segmentation allows independent control of each etching step, improving critical dimension uniformity while maintaining high functional density.
Solution Approach 2:
The patent applies different masking layer configurations to different regions of the substrate. The first masking layer covers specific areas while leaving other areas exposed, and the second masking layer similarly provides region-specific protection. This local quality approach enables precise control of etching in different zones, ensuring uniform critical dimensions across the entire wafer despite varying feature sizes.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct modular steps: first recess formation, first masking layer deposition, second recess formation, and second masking layer deposition. Each module can be independently optimized and controlled, making the overall complex process more manageable and repeatable, thereby maintaining production efficiency despite increased device density.
Solution Approach 2:
The first masking layer is deposited and patterned before the second etching process begins, preparing the substrate in advance for the next fabrication step. This preliminary action ensures that all necessary masking and protection measures are in place before critical etching operations, reducing rework and process variability.
3Manufacturing precision
If multiple masking and covering layers are formed in recesses of varying widths, then critical dimension uniformity improves, but process steps increase
Solution Approach 1:
Each masking layer is specifically designed to address the dimensional control needs of particular recess regions. The first masking layer targets wider recesses requiring greater protection, while the second masking layer addresses narrower recesses. This localized approach ensures optimal critical dimension uniformity for each feature type without applying unnecessary process steps uniformly across the entire substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the critical dimension uniformity of semiconductor device structures, leading to better manufacturing efficiency and cost-effectiveness by ensuring consistent feature sizes and reducing the complexity of the fabrication process.
Implementation Method 1
using anisotropic etching processes to thin and remove these layers
Implementation Method 2
depositing a covering layer in the recess. The covering layer conformally covers inner walls and bottom surfaces of the recess
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.