Semiconductor Device Recesses for Stress Control
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Solution Overview
Problem
The existing methods for fabricating transistors, particularly MOSFETs, require additional manufacturing steps and are costly due to the need for angled dopant implantation, which is difficult to control and can alter the stress of source and drain regions, reducing device performance.
Innovation Solution
The method involves forming recesses in the semiconductor wafer beneath the gate dielectric and filling them with an in-situ doped compound semiconductor material, such as SiGe or SiC, which eliminates the need for angled implantation and enhances carrier mobility by inducing stress in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If angled dopant implantation is used to form source and drain regions, then the doping process can be completed, but the manufacturing time increases and costs increase due to additional manufacturing steps
Solution Approach 1:
The patent performs preliminary actions by forming the gate dielectric and gate structures before creating the source and drain regions. Recesses are etched into the semiconductor substrate at predetermined locations, and dopants are pre-positioned in these recesses before finalization of the source/drain structures. This preliminary preparation eliminates the need for subsequent angled implantation steps, thereby reducing manufacturing time while maintaining doping precision.
2Manufacturing precision
If angled dopant implantation is used to form source and drain regions, then the doping process can be completed, but the stress of source and drain regions is adversely affected, decreasing device performance
Solution Approach 1:
The patent extracts the harmful effect of angled implantation by completely eliminating this process step. Instead of implanting dopants at angles that disrupt the crystal lattice and induce unwanted stress, the method uses in-situ doped semiconductor material deposited conformally over the substrate. This material is then selectively removed from non-recess areas, leaving dopants only in the desired source and drain region locations where they can be properly integrated without causing stress to the channel region.
Solution Approach 2:
The patent replaces the mechanical implantation process (which physically bombard the substrate with dopant ions at high angles) with a chemical deposition process. In-situ doped semiconductor material is deposited using chemical vapor deposition or similar techniques, allowing dopants to be incorporated during the deposition process itself. This substitution eliminates the mechanical disruption to the crystal lattice and the associated stress issues, while maintaining precise dopant placement through selective etching of non-recess areas.
3Manufacturing precision
If additional manufacturing steps are added for dopant implantation, then doping can be achieved, but the time required to manufacture transistors increases
Solution Approach 1:
The patent merges multiple previously separate processes into a unified approach. The formation of source and drain regions is combined with the gate dielectric and gate manufacturing steps. By forming recesses during the gate structure fabrication process and using the same in-situ doped material deposition for both gate and source/drain regions, the patent eliminates standalone dopant implantation steps. This merging of processes maintains doping accuracy through precise spatial control while significantly reducing the overall manufacturing cycle time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost, improves control over stress in the channel region, and enhances transistor performance by maintaining the intrinsic stress induced by embedded SiGe, thereby increasing carrier mobility.
Implementation Method 1
enhances carrier mobility by inducing stress in the channel region
Data Source
AI summary
Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.