Semiconductor Structure Recesses Enhance Trace Bonding
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Solution Overview
Problem
Bump-on-Trace (BOT) semiconductor structures face challenges with peeling off of metal traces due to thermal expansion mismatch and reduced bonding forces as bump pitches become finer, leading to reliability issues.
Innovation Solution
A semiconductor structure with a recess portion filled with conductive material underlying the conductive trace, enhancing the bonding force between the trace and the substrate, and using conductive pillars for both electrical and mechanical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If BOT structures are used to reduce chip area and manufacturing cost, then integration density improves and cost decreases, but metal traces peel off from the package substrate due to thermal expansion mismatch and reduced bonding forces
Solution Approach 1:
The patent introduces a recess portion that extends downward from the substrate surface, transforming a two-dimensional surface bonding problem into a three-dimensional embedded structure. This vertical dimension provides additional bonding area and mechanical interlocking, preventing trace peeling while maintaining the BOT structure's area efficiency
Solution Approach 2:
The conductive trace is nested within the recess portion of the substrate, creating a hierarchical structure where the trace is embedded in the substrate rather than merely surface-mounted. This nesting provides mechanical support and enhances bonding without requiring additional external components
2Area of moving object
If bump pitch is reduced to increase integration density, then more components fit on the chip, but bonding force between conductive traces and package substrate decreases causing trace peeling
Solution Approach 1:
By creating recess portions that extend vertically into the substrate, the patent compensates for the reduced horizontal bonding area available at finer bump pitches. The vertical depth of the recess provides additional bonding surface area, maintaining adequate bonding strength even when horizontal dimensions are minimized
Solution Approach 2:
The recess portions are strategically positioned at specific locations where bonding is critical, concentrating enhanced bonding strength where needed rather than uniformly increasing substrate thickness. This allows fine pitch dimensions elsewhere while maintaining local bonding strength at bump locations
3Ease of manufacture
If conventional BOT structures are used without recess portions, then manufacturing is simpler, but thermal expansion mismatch causes stress on metal traces leading to peeling
Solution Approach 1:
The recess portions are pre-formed in the substrate before trace deposition, creating a stress-absorbing structure in advance. This pre-prepared geometry provides compliance and stress distribution pathways that cushion against thermal expansion forces before they can cause trace peeling
Solution Approach 2:
The patent modifies the substrate geometry parameter by introducing controlled recesses, changing the mechanical compliance and stress distribution characteristics. This geometric parameter change allows the substrate to better accommodate thermal expansion forces without compromising manufacturing feasibility
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar.