Semiconductor Structure With Recessed Die And Bonding Member

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Solution Overview

Problem

The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues such as poor electrical interconnection, component delamination, and inaccurate placement, which cause yield loss and material wastage, thereby increasing manufacturing costs.

Innovation Solution

A semiconductor structure is designed with a substrate having a recess, where a first die is partially disposed within the recess and bonded with a second die using a bonding member, reducing gaps and enhancing electrical connections, and potentially omitting underfill materials to minimize stress and improve signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the semiconductor device is miniaturized to reduce size, then the device size is reduced, but the manufacturing complexity increases and yield loss increases

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing complexity
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The substrate is divided into multiple recesses, and the semiconductor device is segmented into multiple dies that are disposed in different recesses. This segmentation allows each die to be manufactured and tested independently, reducing the impact of manufacturing complexity and yield loss on the entire device while maintaining miniaturization benefits.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple manufacturing operations are implemented on a small semiconductor device, then device functionality is enhanced, but manufacturing complexity increases and yield loss increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The device is segmented into multiple functional dies, each performing specific operations. This allows different manufacturing processes to be applied to different dies independently, reducing the cumulative complexity and yield loss associated with implementing multiple manufacturing operations on a single integrated device.

Inventive Principle:
Principle #1Segmentation

3Reliability

If gaps between dies are reduced to enhance electrical connections, then electrical interconnection quality is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical interconnection qualityVSAvoidgap control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A bonding member is introduced as an intermediary element between adjacent dies to fill gaps and establish electrical connections. This mediator approach relaxes the manufacturing precision requirements for gap control while ensuring reliable electrical interconnection, as the bonding member compensates for variations in die placement accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Stability of the object's composition

If underfill materials are omitted to reduce stress, then component delamination is reduced, but electrical connection reliability may be affected

Engineering Contradiction:
Improvestress reductionVSAvoidelectrical connection reliability
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The bonding member serves as an intermediary that simultaneously provides mechanical support to reduce stress and establish electrical connections between dies. This eliminates the need for separate underfill materials while maintaining both stress reduction and electrical connection reliability through the integrated functionality of the bonding member.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20180005992A1Semiconductor structure and a manufacturing method thereof
Publication Date: 2018.01.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20180005992A1 patent drawing
  • US20180005992A1 patent drawing
  • US20180005992A1 patent drawing

AI summary

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member.