Semiconductor Device Recessed Dielectric for Complete Dicing
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Solution Overview
Problem
The existing semiconductor device fabrication process faces challenges with incomplete cuts and peeling issues due to varying strength characteristics of multiple dielectric layers in the cutting region, which can lead to inefficient separation of semiconductor chips and circuits.
Innovation Solution
The implementation of a semiconductor device design that includes a semiconductor substrate with a lower dielectric layer and an upper dielectric layer, where the upper dielectric layer has recessed portions and redistribution pads connected to chip pads, facilitating a more precise and complete cut during the separation process by managing the strength differences between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dielectric layers are used in the cutting region, then the semiconductor device can achieve better electrical isolation and signal integrity, but the varying strength characteristics of these layers cause incomplete cuts and peeling during the separation process
Solution Approach 1:
The patent applies preliminary action by forming a recessed portion in the upper dielectric layer at the cutting region before the dicing process. This recessed structure is created in advance to address the strength differential issue, allowing the cutting blade to access the lower dielectric layer more easily and complete the cut without causing peeling of the upper dielectric layer.
Solution Approach 2:
The patent applies local quality by creating a recessed portion specifically at the cutting region of the upper dielectric layer, rather than uniformly thinning the entire layer. This localized modification maintains the electrical isolation properties of the upper dielectric layer in non-cutting regions while providing improved cutability only where needed, thus resolving the contradiction between reliability and manufacturing precision.
2Ease of manufacture
If the upper dielectric layer is made thinner to facilitate cutting, then the separation process becomes easier, but the electrical isolation and protective functions of the dielectric layer are compromised
Solution Approach 1:
The recessed portion is formed in advance at the cutting region, creating a localized thinning that facilitates the dicing process. This preliminary modification allows the cutting blade to access the lower dielectric layer without requiring the entire upper dielectric layer to be thin, thus maintaining electrical isolation properties in non-cutting areas while enabling easy cutting at the scribe line.
Solution Approach 2:
Instead of uniformly thinning the upper dielectric layer across the entire substrate, the patent applies local quality by creating the recessed portion only at the cutting region. This selective thinning maintains the protective and isolating functions of the upper dielectric layer in chip regions while providing cutting accessibility only where the scribe line is located, resolving the contradiction between ease of manufacture and reliability.
3Manufacturing precision
If a recessed portion is created in the upper dielectric layer at the cutting region, then complete cuts are achieved without peeling, but the fabrication process becomes more complex
Solution Approach 1:
The recessed portion is formed as part of the preliminary processing steps before dicing, integrating the thickness modification into the existing fabrication flow. By performing this action in advance during the dielectric layer formation or planarization stages, the patent avoids adding a separate complex post-processing step, thus minimizing the increase in fabrication process complexity while achieving complete cuts without peeling.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.