Semiconductor Device Recessed Element Separation Layer
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Solution Overview
Problem
Current semiconductor devices face challenges in optimizing the performance of periphery circuit transistors and achieving efficient data storage due to limitations in three-dimensional memory cell array design, particularly in preventing crystal defects during channel semiconductor layer growth.
Innovation Solution
The semiconductor device incorporates a recess process to form the first element separation layer at a lower level than the second and third active regions, allowing for epitaxial growth of the channel semiconductor layer without interface growth limits, resulting in a channel semiconductor layer free of crystal defects and optimized transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the element separation layer is formed at the same level as the active regions, then the manufacturing process is simpler, but crystal defects occur during channel semiconductor layer growth
Solution Approach 1:
The element separation layer is formed with different levels in different regions: a first level in the first region (under the channel semiconductor layer) and a second level in the second region (exposed after etching). This local differentiation allows the channel semiconductor layer to grow without interface defects in the first region while maintaining manufacturing feasibility.
Solution Approach 2:
The element separation layer is formed at different levels before the channel semiconductor layer is grown. The first element separation layer is formed at a lower level in advance, creating a recess that prevents interface growth defects during subsequent channel semiconductor layer formation.
2Device complexity
If the element separation layer upper surface is at the same level as the active region, then the structure is simpler, but interface growth limits cause crystal defects in the channel semiconductor layer
Solution Approach 1:
The element separation layer is formed with different levels in different regions: a first level in the first region (under the channel semiconductor layer) and a second level in the second region (exposed after etching). This local differentiation allows the channel semiconductor layer to grow without interface growth defects in the first region while maintaining manufacturing feasibility.
Solution Approach 2:
The element separation layer is segmented into two distinct regions with different heights. The first region has a lower level that creates a recess for defect-free channel semiconductor layer growth, while the second region has a higher level that remains exposed. This segmentation resolves the conflict between structural simplicity and crystal quality.
3Manufacturing precision
If a recess process is performed to form the first element separation layer at a lower level, then crystal defects are prevented during channel semiconductor layer growth, but the manufacturing process becomes more complex
Solution Approach 1:
The element separation layer is formed at different levels before the channel semiconductor layer is grown. The first element separation layer is formed at a lower level in advance, creating a recess that prevents interface growth defects during subsequent channel semiconductor layer formation.
Solution Approach 2:
The element separation layer is formed with different levels in different regions: a first level in the first region (under the channel semiconductor layer) and a second level in the second region (exposed after etching). This local differentiation allows the channel semiconductor layer to grow without interface growth defects in the first region while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality channel semiconductor layers with reduced crystal defects, enhancing the performance of periphery circuit transistors and improving data storage capabilities in three-dimensional memory cell arrays.
Implementation Method 1
allowing for epitaxial growth of the channel semiconductor layer without interface growth limits, resulting in a channel semiconductor layer free of crystal defects
Data Source
AI summary
A semiconductor device includes: a periphery circuit structure on a substrate; and a memory cell array on the periphery circuit structure, and including memory cells arranged in a first direction substantially perpendicular to an upper surface of the substrate, wherein the periphery circuit structure includes: a first element separation layer on the substrate and defining a first active region; a channel semiconductor layer on the first active region and at a higher level than an upper surface of the first element separation layer; a first gate structure on the channel semiconductor layer; a second element separation layer on the substrate, defining a second active region and a third active region, and including an upper surface at a higher level than the upper surface of the first element separation layer; a second gate structure on the second active region; and a third gate structure on the third active region.