Semiconductor Devices With Recessed Groove Gate Structures
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Solution Overview
Problem
In the manufacturing of SRAM devices, there is a challenge in achieving optimal threshold voltage control and reducing leakage current between PMOS and NMOS transistors due to differences in their channel layer formation and gate structure design.
Innovation Solution
A method involving partial etching of the substrate and isolation layer to form a recess and groove, allowing for the formation of a silicon-germanium channel layer with a flat top surface and a gate structure that covers both the top surface and sidewall of the channel layer, enhancing the contact area and reducing threshold voltage mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a silicon-germanium layer is formed on the active region to control threshold voltage, then threshold voltage control is improved, but leakage current between PMOS and NMOS regions increases
Solution Approach 1:
The patent divides the gate structure into two distinct parts: a first gate structure formed over the PMOS active region with silicon-germanium channel layer for threshold voltage control, and a second gate structure formed over the NMOS active region without silicon-germanium for leakage reduction. This segmentation allows each transistor type to have optimized channel structures, preventing leakage current while maintaining threshold voltage control where needed.
Solution Approach 2:
The patent applies different material compositions and structures to different regions: silicon-germanium channel layer is selectively formed only in the PMOS active region where threshold voltage control is required, while the NMOS region maintains standard silicon channel to minimize leakage. This local differentiation optimizes performance for each transistor type without compromising the other.
2Ease of manufacture
If a gate structure covers only the top surface of the channel layer, then manufacturing simplicity is maintained, but contact area is insufficient leading to threshold voltage mismatch
Solution Approach 1:
The patent extends the gate structure from covering only the top surface of the channel layer to also covering the sidewalls. The gate insulation layer, work function control layers, and doped polysilicon layer are formed to wrap around the channel layer, providing contact area on both top and lateral surfaces. This three-dimensional gate configuration increases the effective contact area without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of PMOS transistors by decreasing leakage current and reducing the threshold voltage mismatch between PMOS and NMOS transistors, leading to better semiconductor device characteristics.
Implementation Method 1
the etching may be performed using hydrofluoric acid (HF) as an etching solution
Data Source
AI summary
A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.