Semiconductor Interconnect Pads with Recessed Surface Area
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Solution Overview
Problem
Conventional semiconductor device interconnect structures using bumps are prone to de-wetting and exhibit weak joints, leading to reliability issues and manufacturing yield reduction due to limited contact surface area between bump material and conductive pads.
Innovation Solution
The method involves forming a substrate with conductive pads that have an expanded interconnect surface area by creating recesses over the pads, enhancing the bonding area for improved mechanical strength and reliability of the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional bump interconnect structures are used, then the manufacturing process is simple, but the joint strength is weak and de-wetting occurs
Solution Approach 1:
The patent transitions from a conventional planar pad surface to a three-dimensional recessed pad structure. By creating recesses in the conductive pad, the interconnect surface area is expanded into the vertical dimension, allowing bump material to flow into and bond within the recesses. This dimensional change significantly increases the bonding interface area and mechanical interlocking, thereby enhancing joint strength without proportionally increasing overall device complexity.
Solution Approach 2:
The recessed pad structure creates a porous-like geometry with internal cavities and increased surface area. The bump material penetrates into these recesses during bonding, creating a mechanically interlocked joint similar to how porous materials provide enhanced bonding surfaces. This approach increases the effective bonding area and prevents de-wetting by providing multiple bonding interfaces within the recesses.
2Manufacturing precision
If the contact surface area between bump material and conductive pad is limited, then the manufacturing process is simple, but manufacturing yield is reduced
Solution Approach 1:
The patent addresses the surface area limitation by utilizing the vertical dimension through recesses. Instead of simply enlarging the pad footprint, the design creates downward extensions into the pad layer, effectively multiplying the bonding surface area available for bump material contact. This dimensional approach increases the bonding interface without proportionally increasing the overall pad footprint, thereby improving manufacturing yield while controlling the increase in interconnect surface area.
3Temperature
If conventional interconnect structures are used, then the device footprint is small, but heat dissipation is insufficient
Solution Approach 1:
The recessed pad structure provides an additional thermal conduction pathway by extending the conductive material vertically into the recesses. This three-dimensional conductive network increases the effective thermal interface area between the bump interconnect and the underlying conductive pad, enhancing heat dissipation capability. The increased surface area within the recesses allows for more efficient thermal coupling without requiring a larger overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The expanded interconnect surface area increases joint mechanical strength, wettability, and heat dissipation, reducing voids and enhancing the alignment between bumps and conductive pads, thereby improving the reliability and efficiency of semiconductor device interconnects.
Implementation Method 1
The expanded interconnect surface area increases joint mechanical strength, wettability, and heat dissipation
Implementation Method 2
The expanded interconnect surface area increases joint mechanical strength, wettability, and heat dissipation
Data Source
AI summary
A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.