Semiconductor Recesses for Enhanced Carrier Mobility
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Solution Overview
Problem
In the development of MOS transistors, increasing the driving current remains a challenge as the semiconductor processes advance to the very deep sub-micron era, and existing strained silicon layers with SiGe or SiC epitaxial structures do not effectively enhance carrier mobility and stress induction in gate channels.
Innovation Solution
A semiconductor structure and process that forms recesses in a substrate and dual spacer with specific tip geometries, allowing for the formation of epitaxial structures with increased stress induction, including a gate, dual spacer, and recesses with acute upper and lower tips, enabling improved epitaxial structure efficacy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional strained silicon layers with SiGe or SiC epitaxial structures are used, then lattice strain is introduced to alter band structure, but the stress induction in gate channels is insufficient to effectively enhance carrier mobility
Solution Approach 1:
The patent transitions from conventional planar epitaxial structures to three-dimensional protruding epitaxial structures that extend vertically from the substrate surface. This dimensional change allows the epitaxial structures to induce stress more effectively in the gate channel region, thereby enhancing carrier mobility without requiring complex material compositions
Solution Approach 2:
The patent modifies the geometric parameters of the epitaxial structures by controlling their height, width, and position relative to the gate channel. By optimizing these dimensional parameters, the stress induction effect is maximized, improving carrier mobility while maintaining a relatively simple epitaxial structure configuration
2Speed
If the sizes and shapes of epitaxial structures are optimized to affect stresses in gate channel, then transistor speed performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning of the epitaxial structure positions and dimensions before the actual epitaxial growth process. By pre-defining the geometric parameters through lithography and etching steps, the subsequent epitaxial growth can proceed with standard precision, achieving the desired stress distribution without requiring excessive manufacturing precision
3Reliability
If epitaxial structures are formed closer to or with different configurations relative to the gate, then stress induction efficacy improves, but device complexity increases
Solution Approach 1:
The patent introduces epitaxial structures with specific geometric characteristics only in the regions where stress induction is most beneficial, particularly near the gate channel area. The protruding epitaxial structures are positioned and dimensioned to create localized stress fields that enhance carrier mobility in the critical transport region without requiring complex configurations throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described process enhances the stress induction in gate channels by forming epitaxial structures with a W-shaped cross-sectional profile, thereby improving the efficacy of MOS transistors by increasing carrier mobility and device performance.
Implementation Method 1
An etching process is performed on the substrate and the dual spacer to form two recesses in the substrate and the dual spacer beside the gate
Implementation Method 2
By putting a strain on a semiconductor crystal, the speed at which charges move through that crystal is altered
Implementation Method 3
a biaxial tensile strain occurs in the epitaxy silicon structure due to the silicon germanium or silicon carbide epitaxial structure which has a larger or smaller lattice constant than silicon
Implementation Method 4
a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) epitaxial structure or a silicon carbide (SiC) epitaxial structure
Data Source
AI summary
A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.