Semiconductor Recessing Control via Atomic Layer Segmentation

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Solution Overview

Problem

Conventional semiconductor device fabrication methods face challenges in achieving uniformity and control during recessing processes, particularly when forming borderless source/drain contacts, as the etch process is difficult to replicate uniformly across multiple gates on a wafer substrate, leading to issues like gate-to-source/drain shorting and residual etching chemicals causing unintended material removal.

Innovation Solution

The method involves preparing a limited amount of the structure for removal, typically less than ten atomic layers, and performing a controlled removal process to form a recess at the upper portion of the structure, repeating these steps to achieve a preselected depth with enhanced precision, using surface treatment and etching chemistry to selectively remove an intermediate etchable layer without affecting the underlying material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etch process is used for recessing replacement gate electrode, then the etch process can remove material, but it is difficult to control within-wafer and wafer-to-wafer uniformity

Engineering Contradiction:
Improverecess depth uniformityVSAvoidprocess repeatability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the recessing process into multiple controlled steps: forming an intermediate etchable layer, selectively removing limited amounts (less than ten atomic layers) in repeated cycles, and using surface treatment to prepare only the necessary portion for removal. This segmentation enables precise control over recess depth and improves uniformity across wafers by breaking down a single uncontrolled etch into multiple controlled removal cycles.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If direct etching without landing is used to recess replacement gate electrode, then material removal can be achieved, but etch rate control and WIW variation become extremely difficult

Engineering Contradiction:
Improverecessing process simplicityVSAvoidetch rate control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces an intermediate etchable layer as a mediator between the replacement gate electrode and the etch process. This intermediate layer allows for controlled removal of material in precise increments while protecting the underlying fill material. The surface treatment step prepares this intermediate layer for selective removal, enabling precise etch rate control without directly etching the gate electrode itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If conventional recessing process is used for aluminum, then material removal can be achieved, but residual etching chemicals cause etching to continue beyond the desired stopping point

Engineering Contradiction:
Improvematerial removal efficiencyVSAvoidrecess depth accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies surface treatment as a preliminary action before the removal process. This surface treatment prepares only the limited amount of intermediate etchable layer that needs to be removed in each cycle, preventing residual chemicals from affecting deeper layers. By prepping only the necessary surface portion, the process stops precisely at the desired depth without over-etching caused by residual chemicals.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides improved within-wafer and wafer-to-wafer uniformity, ensuring precise control over the recessing process, reducing the risk of material degradation and shorting issues, and enabling the formation of self-aligned contacts with enhanced reliability.

Implementation Method 1

performing a removal process to remove the limited amount of the structure... using surface treatment and etching chemistry to selectively remove an intermediate etchable layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS8617973B2Semiconductor device fabrication methods with enhanced control in recessing processes
Publication Date: 2013.12.31 GLOBALFOUNDRIES US INC
  • US8617973B2 patent drawing
  • US8617973B2 patent drawing
  • US8617973B2 patent drawing

AI summary

Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure.