Semiconductor Packaging with Redistribution Layer and Adhesive Mounting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device manufacturing techniques face challenges in miniaturization and packaging efficiency, particularly in creating smaller scales for integrated circuit packaging, chip stacking, and ensuring reliable electrical connections and encapsulation of semiconductor chips.
Innovation Solution
The method involves using a carrier with adhesive tape to mount semiconductor chips and voltage generating units, applying an encapsulating material, and creating a redistribution layer with metal and dielectric layers to facilitate electrical connections and extend contact points beyond the chip outline, allowing for increased packaging density and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used, then manufacturing simplicity is maintained, but device size cannot be sufficiently miniaturized
Solution Approach 1:
The patent combines multiple functional elements (semiconductor chips, voltage generating units, encapsulation, and electrical connections) into a single integrated package structure. This merging approach enables miniaturization by eliminating the need for separate circuit boards and external components, directly resolving the contradiction between reducing device size and maintaining manufacturing simplicity.
Solution Approach 2:
The patent extends contact points beyond the chip outline in the lateral dimension and stacks multiple chips and voltage generating units in the vertical dimension. This multi-dimensional arrangement increases packaging density and enables further miniaturization while managing the complexity through systematic spatial organization.
2Reliability
If contact points are extended beyond chip outline, then electrical connectivity is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies adhesive tape to the carrier before mounting the semiconductor chips, establishing a predetermined positioning system. This preliminary action creates reference marks and alignment features that guide subsequent bonding and connection processes, thereby enhancing electrical connectivity while managing manufacturing precision requirements through pre-established alignment protocols.
3Productivity
If multiple chips are stacked, then packaging density increases, but encapsulation reliability becomes more difficult to ensure
Solution Approach 1:
The patent implements a stacked configuration where semiconductor chips and voltage generating units are arranged in vertical layers, with each layer nested within the overall package structure. This nesting approach increases packaging density by utilizing three-dimensional space efficiently while maintaining encapsulation reliability through systematic layer-by-layer bonding and sealing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of compact, efficient semiconductor devices with enhanced electrical connectivity and increased contact point density, supporting diverse applications such as mobile devices and sensors without the need for traditional circuit boards.
Implementation Method 1
a carrier with adhesive tape to mount semiconductor chips and voltage generating units
Implementation Method 2
applying an encapsulating material
Implementation Method 3
creating a redistribution layer with metal and dielectric layers to facilitate electrical connections and extend contact points beyond the chip outline
Data Source
AI summary
A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.


