Semiconductor Redistribution Structure for Lower IR Loss

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Solution Overview

Problem

The semiconductor industry faces challenges with increased IR losses in semiconductor devices due to resistive signal paths, which lead to thermal losses and instability in VCC levels, affecting device performance and accuracy.

Innovation Solution

The implementation of an adaptive redistribution structure with adjustable via structures allows for the maintenance of IR characteristics while enabling geometric adjustments between semiconductor chip connections, reducing resistive losses and improving signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but IR losses and thermal losses increase due to longer resistive signal paths

Engineering Contradiction:
Improveintegration densityVSAvoidIR losses
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent segments the signal path into multiple shorter pathways by introducing additional via structures and conductive layers. Instead of a single long resistive path, the signal can travel through multiple segmented paths with lower individual resistance, thereby reducing total IR losses while maintaining high integration density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes three-dimensional redistribution structures with multiple conductive layers and via structures to create alternative signal pathways in the vertical dimension. This dimensional approach allows signals to bypass long horizontal resistive paths by traveling through stacked conductive layers, reducing IR losses without sacrificing integration density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but stability of VCC levels deteriorates due to resistive losses

Engineering Contradiction:
Improveintegration densityVSAvoidVCC level stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The power distribution network is segmented into multiple parallel pathways using additional via structures and conductive layers. This segmentation reduces the equivalent resistance of power paths, improving voltage stability and reducing VCC level fluctuations across the chip

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges multiple conductive layers and via structures into a unified three-dimensional power distribution network. This combining of parallel conductive paths reduces overall resistance and improves power delivery stability, ensuring stable VCC levels throughout the high-density integrated circuit

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If fixed via structures are used in the redistribution structure, then manufacturing is simplified, but adaptability to different connection geometries is reduced

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidgeometric adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent introduces adjustable via structures that can be dynamically positioned or configured during the manufacturing process. These via structures can be selectively formed or removed based on the specific geometric requirements of different chip connections, providing adaptability while maintaining a relatively simple base manufacturing process

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The redistribution structure incorporates universal via structures that can serve multiple functions and adapt to different connection geometries. These multi-functional via structures can be configured to connect different layers and provide flexible routing options, enabling the same basic structure to accommodate various chip layouts and connection requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240282589A1Semiconductor devices and methods of manufacturing thereof
Publication Date: 2024.08.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240282589A1 patent drawing
  • US20240282589A1 patent drawing
  • US20240282589A1 patent drawing

AI summary

A method includes providing a semiconductor chip with a plurality of first connector structures disposed on a topmost one of a plurality of metallization layers. The method includes forming a redistribution structure comprising a plurality of conductive layers and a plurality of via structures, adjacent ones of the plurality of conductive layers being connected through at least a corresponding one of the plurality of via structures. The method includes bonding the plurality of first connector structures to the redistribution structure. The method includes bonding the redistribution structure to a carrier substrate through a plurality of second connector structures. Forming the redistribution structure includes laterally rotating a first one of the plurality of via structures around a second one of the plurality of via structures, the first via structure being vertically above the second via structure.