Semiconductor Redistribution Layer via Groove and Via
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Solution Overview
Problem
The additional redistribution layer structure in semiconductor devices affects the RLC performance, and there is a need to improve this performance while maintaining a low manufacturing cost.
Innovation Solution
A semiconductor structure with a redistribution layer comprising an oxide layer, a nitride layer, a dielectric layer, a groove, and a through via, where the dielectric layer is thicker than the oxide and nitride layers, and the through via extends vertically through these layers to improve connectivity and reduce capacitance, utilizing a mature through silicon via process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a redistribution layer structure is added to redistribute electrodes, then the electrode connectivity and layout are improved, but the RLC performance deteriorates due to increased capacitance
Solution Approach 1:
The redistribution layer structure is segmented into multiple functional layers: a first dielectric layer for insulation, a groove structure for capacitance reduction, and a second dielectric layer for planarization. This segmentation allows each layer to perform its specific function optimally, reducing overall capacitance while maintaining connectivity.
Solution Approach 2:
A groove structure is extracted from the dielectric layer, creating a void space that removes parasitic capacitance-forming material. This extraction directly reduces the capacitance between the electrode and the redistribution layer, improving RLC performance while preserving the electrode redistribution function.
2Shape
If the dielectric layer thickness is increased to improve planarization, then the surface flatness is improved, but the manufacturing cost increases
Solution Approach 1:
The dielectric structure is segmented into two layers with different thicknesses. The first dielectric layer provides the necessary insulation, while the second dielectric layer provides additional planarization. This segmentation achieves the required surface flatness without requiring a single excessively thick dielectric layer, optimizing material usage and manufacturing cost.
Solution Approach 2:
The second dielectric layer is applied selectively to areas requiring additional planarization. By providing localized planarization rather than uniformly thickening the entire dielectric structure, the manufacturing cost is reduced while still achieving the required surface flatness for subsequent processing steps.
Data Source
AI summary
A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.