Semiconductor Device Redistribution Layer Noise Control
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Solution Overview
Problem
Semiconductor devices face challenges in managing simultaneous switching noise (SSN) during signal transmission, which can lead to increased power supply requirements and reduced operating reliability.
Innovation Solution
The semiconductor device incorporates a layered structure with redistribution layers and conductive patterns, including under-bump pads, die pads, and a grouping pattern, to enhance electrical characteristics and operating reliability by optimizing power and ground circuit connections and providing structural protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply requirements are increased to prevent simultaneous switching noise, then SSN is reduced, but device complexity and power consumption increase
Solution Approach 1:
The power supply network is segmented into multiple independent power supply lines and ground lines, allowing separate control and optimization of each path. This segmentation enables localized power management that reduces overall power requirements while maintaining noise control through dedicated pathways.
Solution Approach 2:
Redistribution layers act as intermediary structures between the substrate and bonding pads, providing impedance matching and signal conditioning that reduces noise without requiring increased power supply levels. The intermediary layers transform the electrical characteristics to achieve noise reduction through design rather than brute-force power increases.
2Reliability
If more conductive patterns and redistribution layers are added to improve electrical characteristics, then resistance is reduced and voltage supply is more uniform, but device complexity increases
Solution Approach 1:
Multiple conductive patterns are merged into integrated redistribution layer structures that perform multiple functions simultaneously - power distribution, signal routing, and noise filtering. This merging reduces the total number of discrete components while achieving the desired electrical characteristics through consolidated multi-functional layers.
Solution Approach 2:
The redistribution layers are designed with multi-functionality, serving as power supply lines, ground references, and signal transmission paths simultaneously. Each layer is configured to perform multiple electrical functions, reducing the need for separate dedicated structures and thereby lowering overall device complexity while improving electrical performance.
3Area of stationary object
If bonding pads are positioned closer to the substrate for compact design, then area is reduced, but resistance increases and voltage supply uniformity decreases
Solution Approach 1:
The connection path between bonding pads and substrate is extended into the vertical dimension through multiple redistribution layers stacked in sequence. This dimensional transition allows short horizontal distances (maintaining compact area) while providing long vertical pathways for electrical connection, achieving low resistance through increased path length in the vertical dimension rather than horizontal expansion.
Solution Approach 2:
Multiple conductive layers are nested vertically within each other, with each layer providing additional conductive pathways and parallel current routes. This nesting creates redundant parallel paths that reduce overall resistance and improve current distribution uniformity while maintaining a compact footprint, as the nested structure utilizes vertical space rather than horizontal expansion.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an integrated device ort the semiconductor substrate, a first redistribution layer on the semiconductor substrate, the first redistribution layer having first conductive patterns electrically connected to the integrated device, a second redistribution layer on the first redistribution layer, the second redistribution layer having second conductive patterns connected to the first conductive patterns, and third conductive patterns on a top surface of the second redistribution layer. The third conductive patterns include pads connected to the second conductive patterns, under-bump pads spaced apart from the pads, a grouping pattern between the pads and an outer edge of the second redistribution layer, and wiring lines that connect the under-bump pads to the pads and connect the pads to the grouping pattern.