Semiconductor Redistribution Layer Adhesion via Hybrid PBO Polyimide
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining reliability and efficiency, particularly in the bonding processes of stacked semiconductor devices, where delamination and high-temperature curing processes can lead to yield losses and reliability issues.
Innovation Solution
The use of a hybrid structure combining polybenzoxazole (PBO) and low-temperature cured polyimide materials in redistribution layers, with specific curing processes and adhesion enhancement techniques, to improve adhesion and reduce delamination risks, allowing for smaller feature sizes and increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-temperature curing processes are used to bond semiconductor devices, then bonding strength is improved, but delamination and reliability issues occur
Solution Approach 1:
The patent applies parameter changes by transitioning from high-temperature curing processes to low-temperature curing processes (e.g., curing at temperatures below 150°C for extended periods). This fundamental parameter change in the curing process allows achieving adequate bonding strength without the harmful effects of high temperatures that cause delamination and reliability issues in stacked semiconductor devices.
Solution Approach 2:
The patent employs composite materials by using hybrid redistribution layers combining polybenzoxazole (PBO) and low-temperature cured polyimide materials. This composite material approach enables the structure to achieve both adhesion enhancement and compatibility with low-temperature curing processes, resolving the contradiction between bonding strength and delamination resistance.
2Manufacturing precision
If feature size is reduced to increase integration density, then more components can be integrated, but adhesion and delamination risks increase
Solution Approach 1:
The patent uses composite materials consisting of PBO and low-temperature cured polyimide in the redistribution layers. This material combination provides enhanced adhesion properties that compensate for the increased delamination risks associated with smaller feature sizes, allowing continued miniaturization while maintaining reliability.
Solution Approach 2:
The patent applies local quality by implementing specific adhesion enhancement techniques at critical interfaces where delamination is most likely to occur. The hybrid material structure provides localized adhesion improvement at the bonding interfaces between stacked devices, addressing the adhesion challenges specific to reduced feature size geometries.
3Volume of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then device footprint is reduced, but bonding process complexity increases
Solution Approach 1:
The patent simplifies the bonding process by changing the temperature parameter from high-temperature to low-temperature curing. This parameter change reduces the complexity of the bonding process by eliminating the need for sophisticated high-temperature process control while still achieving reliable bonds in stacked semiconductor devices with reduced footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with improved adhesion and reduced delamination, achieving smaller feature sizes and enhanced reliability, as demonstrated by increased adhesion values and successful reliability tests such as uHAST and HTS.
Implementation Method 1
improved adhesion and reduced delamination, achieving smaller feature sizes and enhanced reliability
Data Source
AI summary
A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.