Semiconductor Device Redistribution Layer Signal Routing
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving higher integration density and performance while navigating the difficulties of reducing process margins, such as in photolithography, and integrating multiple semiconductor chips on a reduced area without encountering issues like metallic diffusion and substrate cracking during cutting processes.
Innovation Solution
A semiconductor device with a redistribution layer formed using a deposition and patterning process, featuring a conductive pattern that connects center and boundary pads through insulating structures, allowing for efficient signal routing and reducing the need for thick metal layers on boundary regions, thereby facilitating efficient integration and cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick metal layers are used on boundary regions to ensure electrical connection, then electrical reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the thick metal layer requirement from the boundary region by providing electrical connections through the substrate itself. The substrate acts as the primary interconnection medium, eliminating the need for additional thick metal layers that would otherwise be required to ensure reliable electrical connections in boundary regions.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, enables signal transmission, and acts as the primary interconnection medium replacing traditional thick metal layers. This multi-functionality reduces overall device complexity while maintaining electrical reliability.
2Productivity
If multiple semiconductor chips are integrated on a reduced area, then integration density is improved, but the risk of substrate cracking during cutting increases
Solution Approach 1:
The substrate is divided into multiple individual chip regions, each with its own integrated circuit and pad structures. This segmentation allows each chip to be independently handled and tested, reducing the risk of cracking during the cutting and separation process while maintaining high integration density.
Solution Approach 2:
The substrate is designed with sufficient thickness and structural reinforcement before the cutting process to prevent cracking. By preparing the substrate with adequate mechanical strength in advance, the patent enables safe dicing and separation of multiple chips without compromising substrate integrity during fabrication.
3Productivity
If process margins are reduced to achieve higher performance, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the interconnection parameter from thick metal layers to substrate-based connections, which have different dimensional tolerances and manufacturing characteristics. This parameter change allows for relaxed photolithography process margins while achieving the required electrical performance and signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density and performance by efficiently routing signals between semiconductor chips, reducing production costs, and preventing substrate damage during cutting, while maintaining high operational characteristics.
Implementation Method 1
a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, the contact portion filling at least part of the contact hole and the conductive line portion disposed on the first lower insulating structure to connect the contact portion to the bonding pad portion
Data Source
AI summary
A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip. The first lower insulating structure has a top surface positioned at a higher vertical level than that of the second lower insulating structure.