Semiconductor Redistribution Lines with Variable Land Areas
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Solution Overview
Problem
Multi-chip wafer-level chip-size packaging (WL-CSP) faces challenges in reliably connecting semiconductor chips due to warpage caused by thick redistribution lines, leading to potential open faults as the chips stack in opposite directions.
Innovation Solution
The solution involves designing semiconductor devices with redistribution lines that include lands of varying surface areas, where the shortest distance between the outer edges of the second land and electrode is less than that of the first land, and forming electrodes connected to these lands to reduce warpage and improve connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick redistribution lines are used for electrode formation, then electrode strength and conductivity are improved, but warpage of the semiconductor chip occurs
Solution Approach 1:
The patent applies local quality by making the land area variable depending on the location. Specifically, the land area at the connection portion with the electrode is made smaller than the land area at other portions of the redistribution line. This localized variation in land area allows the redistribution line to better accommodate thermal stress and prevent warpage, while still maintaining adequate electrode strength and conductivity at the connection interface.
2Productivity
If semiconductor chips with opposite warpage are stacked, then multi-chip packaging is achieved, but connection reliability deteriorates due to open faults
Solution Approach 1:
The patent applies local quality by making the land area at the connection portion with the electrode is made smaller than the land area at other portions of the redistribution line. This localized variation in land area allows the redistribution line to better accommodate thermal stress and prevent warpage, while still maintaining adequate electrode strength and conductivity at the connection interface.
Solution Approach 2:
The patent applies preliminary anti-action by pre-designing the redistribution line structure with variable land areas to counteract the warpage that will occur during chip stacking. By anticipating the opposite warpage directions of stacked chips, the redistribution line is configured in advance to compensate for these deformations, ensuring reliable electrode connections are maintained despite the opposing warpage forces.
3Ease of manufacture
If uniform land area is used for all redistribution lines, then manufacturing simplicity is maintained, but warpage suppression is insufficient
Solution Approach 1:
The patent applies local quality by making the land area at the connection portion with the electrode is made smaller than the land area at other portions of the redistribution line. This localized variation in land area allows the redistribution line to better accommodate thermal stress and prevent warpage, while still maintaining adequate electrode strength and conductivity at the connection interface.
Data Source
AI summary
A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.