Semiconductor Redistribution Pads for Scribe Line Integrity
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently integrating redistribution pads and connection structures to facilitate data input/output and testing of integrated circuits, particularly in maintaining structural integrity during the chip separation process.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a chip region, edge region, and insulating layers, featuring connection structures and redistribution pads that are strategically spaced and connected to ensure electrical connectivity and minimize area on the scribe line region, allowing for efficient data transfer and testing while preventing non-uniform cutting and cracking during chip separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If redistribution pads are disposed close to connection structures to minimize area, then area on scribe line region is reduced, but structural integrity during chip separation deteriorates causing non-uniform cutting and cracking
Solution Approach 1:
The semiconductor substrate is divided into a chip region and a scribe line region, with redistribution pads strategically positioned within the chip region and connection structures positioned in the edge region. This segmentation allows the scribe line region to be minimized while maintaining structural integrity by keeping critical pads away from the cutting path.
Solution Approach 2:
The patent utilizes vertical layering with multiple insulating layers to separate redistribution pads from connection structures in the vertical dimension while maintaining their functional connectivity. This dimensional approach allows compact area utilization without compromising structural strength during separation.
2Area of stationary object
If connection structures are spaced closely to reduce device footprint, then area is minimized, but electrical connectivity and signal integrity worsen
Solution Approach 1:
Multiple insulating layers are introduced to create vertical separation between connection structures, allowing them to be spaced closely in the horizontal plane while maintaining electrical integrity through controlled via connections in the vertical dimension.
Solution Approach 2:
Insulating layers with controlled via structures act as intermediaries between closely spaced connection structures, ensuring proper electrical connectivity while maintaining minimal spacing. The via structures provide precise electrical pathways through the insulating layers.
3Reliability
If redistribution pads are positioned over chip region to improve connectivity, then electrical connection is improved, but area on scribe line region increases
Solution Approach 1:
The device is segmented into functional regions: chip region for active circuits and pad structures, edge region for connection structures, and scribe line region for separation. This segmentation allows redistribution pads to be positioned over the chip region for optimal connectivity while keeping the scribe line region minimal.
Solution Approach 2:
Multiple insulating layers enable vertical stacking of pad structures over the chip region, improving electrical connectivity through shorter horizontal traces while maintaining compact horizontal footprint, thus minimizing scribe line area.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.