Semiconductor Package With Redistribution Structure And Stacked Dies
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving higher reliability, finer interconnection pitches, and cost-effective manufacturing, particularly in wafer level chip scale packages (WLCSP), where traditional solutions like BGA packages have limitations in signal transmission speed and packaging efficiency.
Innovation Solution
The semiconductor device incorporates a redistribution structure with specific trace configurations and connection layouts between dies, eliminating solder bumps and utilizing molding materials to enhance interconnection density and reliability, while maintaining cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional BGA packages are used, then connection density is improved, but signal transmission speed deteriorates due to longer trace lengths
Solution Approach 1:
The patent transitions from a two-dimensional BGA connection array to a three-dimensional stacked die configuration. Multiple dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling short-distance vertical signal transmission while maintaining high connection density. This dimensional change allows signals to travel shorter distances through the vertical stacking approach rather than across a large planar array.
2Quantity of substance
If integration density within die is increased, then functional capability is improved, but packaging complexity increases
Solution Approach 1:
The patent divides a highly integrated system into multiple separate dies, each containing specific functional blocks. These segmented dies are then stacked and interconnected using TSVs and redistribution layers. This segmentation allows each die to be optimized for its specific function while the overall system achieves high integration density through vertical stacking, thereby managing packaging complexity through modular design.
Solution Approach 2:
The patent implements a nested structure where multiple dies are stacked vertically within a compact package footprint. Each die is nested within the three-dimensional structure, with lower dies supporting upper dies. This nesting approach enables high integration density by utilizing vertical space efficiently while keeping the overall package size compact, managing complexity through hierarchical organization.
3Ease of manufacture
If solder bumps are eliminated in favor of direct die-to-redistribution connection, then manufacturing cost is reduced, but connection reliability may worsen
Solution Approach 1:
The patent introduces redistribution layers (RDLs) as intermediary structures between the dies and external connections. These RDLs provide robust electrical pathways and mechanical support, replacing the need for solder bumps while maintaining connection reliability. The RDLs are integrated into the substrate and provide stable, low-inductance connections that are more reliable than solder joints, thereby achieving both cost reduction and reliability maintenance.
4Quantity of substance
If finer interconnection pitches are achieved, then connection density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves fine interconnection pitches by transitioning to vertical interconnections through TSVs rather than lateral connections in a planar array. The vertical dimension allows for smaller pitch dimensions to be achieved more easily, as the precision requirements are shifted from lateral alignment to vertical stacking alignment. This dimensional change enables finer effective pitches while managing manufacturing precision through specialized vertical alignment processes.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.