Semiconductor Package Redistribution Via Wiring Alignment
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in aligning and forming redistribution patterns, particularly in the integration of via and wiring regions, which can lead to spatial restrictions and misalignment issues during the fabrication process.
Innovation Solution
A semiconductor package design that incorporates a redistribution structure with multiple insulating layers and redistribution patterns, where the via and wiring regions are formed simultaneously using a single process, ensuring positive alignment and reducing spatial restrictions by eliminating the need for extra alignment features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If via and wiring regions are formed through separate photolithography processes, then each region can be independently designed, but alignment errors occur between the two regions leading to misalignment issues
Solution Approach 1:
The patent combines the formation of via regions and wiring regions into a single photolithography process by defining both regions within one photoresist layer. This merging eliminates the need for separate alignment steps between via and wiring regions, thereby resolving the alignment precision issue while maintaining design independence through selective etching processes.
2Productivity
If multiple separate photolithography processes are used to form wiring and via regions, then each region can be optimized independently, but the fabrication process becomes more complex and time-consuming
Solution Approach 1:
The invention merges multiple photolithography processes into a single process by forming both wiring and via regions in one photoresist layer. This reduces the number of fabrication steps and improves productivity while maintaining the ability to independently optimize each region through subsequent selective etching operations.
Solution Approach 2:
The patent applies segmentation by using different etching conditions to selectively remove photoresist in via regions versus wiring regions after single-layer formation. This allows independent optimization of each region's geometry and properties while maintaining the benefits of a simplified single-step photolithography process.
3Manufacturing precision
If extra alignment features are added to ensure proper positioning, then alignment accuracy improves, but the device structure becomes more complex and spatial freedom is restricted
Solution Approach 1:
The patent eliminates the need for extra alignment features by merging via and wiring region formation into a single photolithography process. The inherent registration of features within one photoresist layer provides sufficient alignment accuracy without requiring additional alignment structures, thereby maintaining structural simplicity and spatial freedom.
Data Source
AI summary
A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.