Semiconductor Redistribution Structure for Wafer Bonding
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in scaling down dimensions while maintaining quality, yield, performance, and reliability, with existing methods facing increased complexity and cost due to misalignment of conductive pads during wafer bonding, requiring complex and costly processes to achieve matching layouts.
Innovation Solution
A semiconductor device design featuring a redistribution structure that electrically couples wafers with the same layout using a wafer-to-wafer hybrid bonding process, allowing for direct bonding without carriers and reducing process complexity by re-routing conductive pads, and the use of through semiconductor vias and interconnect layers for enhanced electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer bonding methods are used to bond wafers with misaligned conductive pads, then electrical coupling can be achieved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent introduces a redistribution structure as an intermediary element between the first and second wafers. This redistribution structure includes conductive pads and interconnects that realign and re-route electrical connections, enabling proper electrical coupling despite the misalignment of original conductive pads. The intermediary structure transforms the misaligned connection problem into a solvable routing problem.
Solution Approach 2:
The patent adds an intermediate layer (redistribution structure) between the two wafers, effectively using the vertical dimension to resolve the horizontal misalignment issue. By introducing this additional layer, the system can accommodate pad misalignment without requiring precise lateral positioning, thus reducing fabrication complexity.
2Manufacturing precision
If complex processes are used to achieve matching layouts during wafer bonding, then alignment precision improves, but manufacturing cost increases
Solution Approach 1:
The redistribution structure serves as a mediator that decouples the alignment requirement from the bonding process. Instead of requiring precise alignment between misaligned pads, the redistribution structure provides new alignment references, allowing standard bonding processes to achieve sufficient alignment precision without complex additional steps.
Solution Approach 2:
The redistribution structure is formed in advance on one of the wafers before bonding. This preliminary formation of the redistribution pattern allows the subsequent bonding process to proceed with standard alignment tolerances, avoiding the need for complex real-time alignment adjustments during bonding.
3Device complexity
If direct wafer-to-wafer bonding is performed without carriers, then process simplicity improves, but handling and alignment difficulty increases
Solution Approach 1:
The redistribution structure acts as an intermediary that provides mechanical and electrical interface between the wafers. This structure can be designed to facilitate handling, for example by providing robust bonding areas or mechanical features that simplify the bonding operation, thereby reducing handling difficulty while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and complexity by enabling direct bonding of wafers with the same layout, improving electrical coupling and thermal dissipation, and simplifying the manufacturing process.
Implementation Method 1
bonding a second circuit layer on the first redistribution structure through a wafer-to-wafer hybrid bonding process
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a first substrate, and a first circuit layer positioned on the first substrate, a first redistribution structure positioned on the first circuit layer, and a second semiconductor structure including a second circuit layer positioned on the first redistribution structure, and a second substrate positioned on the second circuit layer. A layout of the first circuit layer and a layout of the second circuit layer are substantially the same and the first redistribution structure is electrically coupled to the first semiconductor structure and the second semiconductor structure.