Semiconductor Redundancy Address Collision Prevention
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Solution Overview
Problem
Semiconductor devices face address collisions when multiple redundancy addresses are stored for the same repair address, leading to potential malfunction due to simultaneous activation of redundancy word lines.
Innovation Solution
Incorporating a repair address storage circuit, address comparison circuit, and word line selection circuit to prioritize and manage multiple repair addresses, preventing simultaneous activation of redundancy word lines by generating distinct select signals for each repair address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple redundancy addresses are stored for the same repair address, then the device can handle more defective memory cells, but address collisions occur causing simultaneous activation of redundancy word lines
Solution Approach 1:
The patent stores priority information alongside repair addresses in the nonvolatile memory circuit before address collisions can occur. This preliminary action allows the address comparison circuit to later identify and prioritize among multiple redundant addresses, preventing simultaneous activation of redundancy word lines while maintaining the ability to handle multiple defective cells.
Solution Approach 2:
The patent introduces a priority signal as an intermediary element between the repair address storage and the redundancy word line activation. This priority signal mediates the conflict resolution process by providing additional comparison criteria to the address comparison circuit, enabling it to select one valid redundancy address over others when collisions occur.
2Adaptability or versatility
If repair addresses are stored multiple times in different locations, then more redundancy options are available, but simultaneous activation of multiple redundancy word lines occurs
Solution Approach 1:
The patent pre-stores priority information with each repair address in the nonvolatile memory circuit. This preliminary organization of data with explicit priority levels simplifies the address management complexity by providing ready-to-use comparison criteria, eliminating the need for complex real-time decision logic when multiple addresses are stored.
Solution Approach 2:
The patent changes the storage parameter from storing only repair addresses to storing tuples of (repair address, priority signal). This parameter change transforms the data structure to include an additional dimension for priority information, which simplifies the management of multiple redundancy options by providing built-in resolution criteria.
3Device complexity
If a simple storage structure is used for repair addresses, then the device complexity is low, but address collisions cannot be prevented
Solution Approach 1:
The patent merges the repair address storage function with the priority signal storage function into a unified nonvolatile memory circuit structure. This combining of functions maintains relative simplicity while enabling collision prevention, as the priority information is stored alongside the addresses rather than requiring separate complex management systems.
Solution Approach 2:
The patent introduces the priority signal as an intermediary element that is stored with the repair address. This intermediary provides the necessary collision prevention capability without significantly increasing overall device complexity, as it integrates seamlessly into the existing address storage and comparison architecture.
Data Source
AI summary
A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address storage circuit may store a first repair address and a second repair address. The address comparison circuit may generate a first comparison signal by comparing an input address and the first repair address, and may generate a second comparison signal by comparing the input address and the second repair address. The word line selection circuit may generate a first redundancy word line select signal corresponding to the first comparison signal and a second redundancy word line select signal corresponding to the second comparison signal, based on the first comparison signal and the second comparison signal.