Semiconductor Redundancy Circuit Fuse Design for Data Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing redundancy circuits in semiconductor memory devices incorrectly determine whether a normal address corresponds to a defective memory cell, leading to reduced reliability in repair operations due to the output of changed data instead of latched data during normal operations.
Innovation Solution
A redundancy circuit and fuse circuit design that blocks the current path between the latch unit and data line during normal operations, ensuring that data latched during boot-up is not altered, by using a storage unit with cross-coupled latch and a driving control unit that forms a current path only during boot-up, and outputs defective address information through a different line during normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the current path between latch unit and data line is maintained during normal operation, then data can be updated, but data integrity is compromised and repair reliability decreases
Solution Approach 1:
The circuit dynamically changes the connectivity state between latch unit and data line based on operation mode. During boot-up operation, the current path is enabled to allow data loading. During normal operation, the current path is blocked to preserve latched data integrity. This dynamic reconfiguration resolves the contradiction by adapting the circuit state to operational requirements.
Solution Approach 2:
A control unit acts as an intermediary between the latch unit and data line, managing the current path connectivity. The control unit receives operation mode signals and selectively enables or disables the current path, preventing direct interaction between the latch unit and data line during normal operation while allowing it during boot-up, thus ensuring data integrity without excessive complexity.
2Device complexity
If the same data line is used for both boot-up and normal operations, then device complexity is reduced, but data corruption occurs during normal operation
Solution Approach 1:
The data line's functional role is dynamically changed based on operation mode. During boot-up, the data line connects to the latch unit for data loading. During normal operation, the connection is blocked and the data line serves other functions. This dynamic usage allows a single data line to serve multiple purposes without causing data corruption.
Solution Approach 2:
The connection between data line and latch unit is periodically enabled only during boot-up operations and disabled during normal operations. This periodic activation ensures that data line usage does not corrupt latched data while still allowing necessary data loading during initialization.
3Reliability
If the current path is blocked during normal operation, then data integrity is maintained, but additional control mechanisms are required
Solution Approach 1:
The control unit performs multiple functions: it manages current path connectivity, interprets operation mode signals, and coordinates between different circuit blocks. By making the control unit multi-functional, the patent avoids adding separate dedicated control circuits for each function, thereby maintaining data integrity without proportionally increasing overall device complexity.
Solution Approach 2:
The control functions for managing the current path are merged with the existing operation mode control logic. The same control unit that manages overall device operation also manages the latch unit connectivity, combining multiple control responsibilities into a single integrated unit rather than adding separate control circuits.
Data Source
AI summary
Disclosed herein is a fuse circuit including a storage unit capable of storing defective address information corresponding to mat information when a boot-up operation is performed, a driving control unit coupled between the storage unit and a first power source terminal, and capable of forming a current path between the storage unit and the first power source terminal in response to the defective address information transferred through a first data line and the mat information transferred through a second data line while blocking the current path between the storage unit and the first power source terminal when a normal operation is performed, and an output unit capable of outputting the defective address information stored in the storage unit when the normal operation is performed.