Semiconductor Integrated Circuit Redundancy Management
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Solution Overview
Problem
Existing semiconductor integrated circuit technologies face challenges in efficiently transferring redundancy address data to memory macros with varying defect rates, as they often require fixed redundancy data bits and complex control mechanisms, leading to inefficient fuse data management and increased complexity.
Innovation Solution
A semiconductor integrated circuit design featuring a plurality of memory macros with redundancy cells, non-volatile memory elements for storing redundancy data, and a transfer control circuit that dynamically transfers redundancy data based on address information, allowing for flexible redundancy data storage and reduced fuse count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fuse box is used to transfer redundancy address data to memory macros, then redundancy management is enabled, but the number of fuses increases and control complexity increases
Solution Approach 1:
The patent combines multiple memory macros into a single memory block with unified redundancy management. Instead of providing separate fuse boxes for each memory macro, the invention merges the redundancy management function at the memory block level, allowing one fuse box to serve multiple memory macros. This reduces the overall number of fuses and simplifies control logic while maintaining comprehensive redundancy coverage across all memory macros in the block.
Solution Approach 2:
The fuse box is designed with universal functionality to manage redundancy for multiple memory macros simultaneously. The redundancy management circuit can dynamically allocate and transfer redundancy data to any memory macro within the block based on defect detection, making the fuse box a multi-functional component rather than a dedicated one-to-one solution. This universality reduces the total fuse count and control complexity.
2Device complexity
If fixed redundancy data bits are allocated to each memory macro, then simplicity is maintained, but adaptability to varying defect rates is reduced
Solution Approach 1:
The patent implements dynamic redundancy allocation where the number of redundancy data bits transferred to each memory macro is not fixed but adapts based on the actual defect situation. The redundancy management circuit can dynamically adjust the amount of redundancy data allocated to each memory macro within the block, allowing the system to optimize fuse usage while providing appropriate redundancy coverage for varying defect rates across different memory macros.
3Manufacturing precision
If redundancy data length varies by memory macro position, then precision is improved, but fuse data management efficiency decreases
Solution Approach 1:
The patent introduces a redundancy management circuit as an intermediary between the fuse box and multiple memory macros. This intermediary component handles the complexity of variable-length redundancy data allocation, managing the transfer of appropriate amounts of redundancy data to each memory macro based on its specific needs. By placing this intelligent intermediary in place, the system achieves precise redundancy allocation without directly burdening the fuse box with complex variable-length management, thereby maintaining efficiency.
Data Source
AI summary
There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.