Semiconductor Chip Reference Voltage Circuit Layout
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Solution Overview
Problem
Existing semiconductor chip designs do not effectively utilize corner regions for element placement, leading to inefficiencies in element arrangement and increased noise due to longer wiring distances between elements in the reference voltage generation circuit.
Innovation Solution
Arranging some elements of the reference voltage generation circuit in corner regions that are typically dead space for IO cells, and placing remaining elements in the core region close to the corner regions, thereby reducing wiring distances and suppressing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If elements of the reference voltage generation circuit are arranged only in the core region, then the wiring distance between elements is reduced, but the number of elements that can be arranged on the chip is limited due to unused corner regions
Solution Approach 1:
The reference voltage generation circuit is divided into multiple elements that are segmented and placed in different locations: some elements are arranged in the corner region while remaining elements are arranged in the core region. This segmentation allows the circuit to utilize both the corner dead space and the core region, thereby increasing the total number of elements that can be arranged on the chip while maintaining reasonable wiring distances through strategic placement.
2Quantity of substance
If corner regions are used for element placement, then the number of elements increases, but the positional relationship between corner region elements and core region elements becomes complex
Solution Approach 1:
Different regions of the chip are assigned different functional qualities: the corner region is utilized for placing specific elements of the reference voltage generation circuit that can tolerate longer wiring distances, while the core region contains remaining elements requiring shorter wiring. This local quality differentiation optimizes the overall layout by matching element placement with regional characteristics, increasing element capacity while managing positional complexity through functional zoning.
Data Source
AI summary
A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.