Semiconductor Refresh Control Block Bank Address Verification
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Solution Overview
Problem
Semiconductor apparatuses face issues with refresh errors due to incorrect bank addresses provided by controllers, leading to potential data damage during refresh operations.
Innovation Solution
A semiconductor apparatus with a refresh control block that updates refresh bank information and activates count control signals based on address count values, allowing for stable and error-free refresh operations across multiple memory banks, independent of the order or number of banks to be refreshed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a controller provides bank addresses for refresh operations, then refresh operations can be performed on specific banks, but refresh errors occur when incorrect bank addresses are provided
Solution Approach 1:
The refresh control block maintains a refresh bank information table that pre-stores the correspondence between bank addresses and bank numbers. Before executing refresh operations, the system checks whether the provided bank address matches the stored information, preventing refresh errors by verifying address validity in advance.
Solution Approach 2:
The system implements a feedback mechanism where the refresh control block continuously monitors and updates the refresh bank information table based on actual refresh operations. When a refresh operation is completed, the corresponding bank address information is updated in the table, ensuring that subsequent refresh operations use accurate and current bank address mappings.
2Reliability
If refresh operations are performed on all banks sequentially, then all memory banks are refreshed, but the refresh process becomes time-consuming and reduces system productivity
Solution Approach 1:
The refresh operation is divided into independent bank-level segments. Instead of treating all banks as a single sequential process, the system can identify and refresh specific banks that require attention based on the refresh bank information table, allowing parallel or selective refresh operations that reduce overall refresh time while maintaining data integrity.
Solution Approach 2:
The system performs refresh operations only on banks that actually need refreshing, rather than forcing a complete refresh of all banks. By checking the refresh bank information table, the system identifies specific banks that require refresh and executes operations only on those banks, reducing unnecessary refresh cycles and improving productivity.
3Manufacturing precision
If the address count value is incremented for each refresh operation, then word lines can be systematically refreshed, but errors occur when bank addresses are incorrect
Solution Approach 1:
Before incrementing the address count value for refresh operations, the system first verifies that the provided bank address matches the stored bank address in the refresh bank information table. This preliminary verification ensures that the address count is only incremented when the bank address is correct, preventing propagation of address errors through the refresh process.
Solution Approach 2:
The system replaces manual or controller-provided address management with an automated verification mechanism. The refresh control block automatically checks bank address validity against the stored refresh bank information table and controls the address count increment accordingly, eliminating reliance on potentially erroneous external address provisioning.
Data Source
AI summary
A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.