Semiconductor Device Fabrication via Region-Dependent Patterning

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Solution Overview

Problem

As integration density of semiconductor devices increases, existing patterning methods, such as double patterning technology, are insufficient for forming patterns smaller than their capability, necessitating the development of more advanced techniques to achieve higher reliability and performance.

Innovation Solution

A method involving the sequential formation of mold layers and spacers on a substrate with different regions, using various etching processes to create region-dependent pattern densities, including quadruple patterning in one region and double patterning in another, with etching-prevention patterns and spacer layers to control etching and pattern formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If double patterning technology is used to form fine patterns, then patterns smaller than minimum feature size can be printed, but the pattern size cannot be reduced further to meet increasing integration density requirements

Engineering Contradiction:
Improvepattern sizeVSAvoidintegration density
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent divides the substrate into multiple regions (first region, second region, third region) and applies different patterning processes to each region. The first region undergoes quadruple patterning to form densely spaced active patterns, while the second region undergoes double patterning to form sparsely spaced active patterns. This segmentation allows each region to be optimized for its specific integration density requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are given different pattern densities tailored to their specific functional requirements. The first region receives a higher pattern density (quadruple patterning) while the second region receives a lower pattern density (double patterning), allowing each region to have the optimal pattern density for its intended use.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If different patterning processes are applied to different regions, then region-dependent pattern densities can be achieved, but the fabrication process complexity increases

Engineering Contradiction:
Improveregion-dependent pattern densityVSAvoidfabrication process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A common lower mold pattern is formed first across the entire substrate before dividing the regions and applying different upper mold patterns. This preliminary formation of the lower mold pattern provides a unified foundation that simplifies subsequent region-specific processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs a nested structure where a first upper mold pattern is formed within the framework of the lower mold pattern, and then a second upper mold pattern is formed within the first upper mold pattern's defined regions. This nested approach allows complex multi-region patterning to be achieved through sequential, organized steps rather than simultaneous complex operations.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the fabrication of semiconductor devices with region-dependent pattern densities, enhancing integration density and performance by enabling the formation of smaller patterns and improving the complexity and reliability of semiconductor devices.

Implementation Method 1

etching an upper portion of the substrate using the lower mold patterns as an etch mask to form active patterns

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS9911828B2Methods of fabricating a semiconductor device
Publication Date: 2018.03.06 SAMSUNG ELECTRONICS CO LTD
  • US9911828B2 patent drawing
  • US9911828B2 patent drawing
  • US9911828B2 patent drawing

AI summary

Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and intermediate mold layers on a substrate, forming first upper mold patterns and first spacers on the first and second regions, respectively, of the substrate, etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively, forming second spacers to cover sidewalls of the first and second intermediate mold patterns, etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns, and etching the substrate using the lower mold patterns as an etch mask to form active patterns.