Semiconductor Register Positioning for Scan Wire Length Reduction

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Solution Overview

Problem

In semiconductor integrated circuit design, the positional relationship between cells related to scan signals is not considered during layout data generation, leading to increased wire length and integration obstacles due to the distance between the scan chain and compression scan circuit.

Innovation Solution

A design apparatus that includes a register position determining module, net list generator, and layout data generator, which determines optimal register positions and changes compression logic to minimize the total wire length of scan wires by aggregating scan chains and compression scan circuits, generating a second net list that reduces wire congestion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cell position is determined in a unit of functional group considering operation signals, then operation functionality is improved, but scan test wire length increases

Engineering Contradiction:

Improveoperation functionalityVSAvoidscan wire length

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent segments the determination process into two phases: first determining cell positions based on functional groups for operation functionality, then adjusting positions within allowable ranges to optimize scan wire length. This segmentation allows both operation reliability and scan test efficiency to be addressed separately and sequentially.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by allowing different cells to have different positional adjustment ranges based on their specific functional group constraints. Each cell's position is optimized locally within its functional group's allowable range, rather than applying a uniform approach across the entire circuit.

Inventive Principle:

Principle #3Local quality

2Ease of operation

If scan chain and compression scan circuit are placed far apart, then operation signal routing is improved, but scan test integration is obstructed

Engineering Contradiction:

Improveoperation signal routingVSAvoidscan test integration

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent introduces dynamic positioning where cell positions are not fixed solely by functional group requirements but can be adjusted within allowable ranges. This dynamic adjustment capability allows the layout to adapt to both operation signal routing needs and scan test integration requirements, resolving the contradiction between the two.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of cell position from a fixed value determined only by functional group to a flexible parameter with an allowable range. This parameter change enables optimization of both operation signal routing and scan wire length by selecting appropriate positions within the allowable ranges.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20130239074A1Apparatus, method and medium storing program for designing semiconductor integrated circuit

Publication Date: 2013.09.12 KK TOSHIBA

AI summary

According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit.