Semiconductor Regulator Transistor Layout for Voltage Drop Reduction
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in maintaining stable supply voltage due to increasing current demands of nonvolatile memories, as multilayered wiring struggles to cope with larger currents and slight voltage drops can compromise operating voltage stability.
Innovation Solution
The design includes a regulator with transistors arranged in a specific layout where input and output voltage pads are aligned along one edge of the semiconductor chip, with parallel branch lines and gates parallel to these pads, reducing sheet resistance and voltage drop by optimizing transistor connections and wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multilayered wiring is used to reduce sheet resistance, then voltage drop is reduced, but the wiring still cannot cope with large currents from high-capacity nonvolatile memories
Solution Approach 1:
The regulator output driver is segmented into multiple parallel transistors (first through fourth transistors), each handling a portion of the total current. This segmentation allows the system to distribute large currents across multiple pathways, reducing the current burden on individual wiring segments while maintaining low overall voltage drop.
Solution Approach 2:
The patent transitions from planar wiring layouts to a three-dimensional stacked transistor configuration. By arranging transistors in multiple layers (first and second transistors in one layer, third and fourth transistors in another layer), the design increases current handling capacity without proportionally increasing wiring area or sheet resistance.
2Use of energy by moving object
If supply voltage VCC is kept close to nonvolatile memory operating voltage to reduce power consumption, then power efficiency improves, but stability is compromised due to slight voltage drops
Solution Approach 1:
The regulator is designed with excess current handling capacity through parallel transistor configurations and robust wiring (first and second main lines with branch lines) that preemptively compensates for voltage drops. This cushioning ensures that even when VCC is close to the memory operating voltage, the regulator can maintain stable output by absorbing current variations without compromising voltage stability.
3Object-affected harmful factors
If series regulators are mounted diagonally to switching regulator to reduce high frequency noise influence, then noise reduction is achieved, but the layout complexity increases
Solution Approach 1:
The patent merges the voltage regulation function into a single integrated regulator block with internally parallel-connected transistors, eliminating the need for separate series regulators positioned diagonally around a switching regulator. This consolidation reduces layout complexity while maintaining noise performance through the inherent shielding effect of the compact transistor arrangement.
Data Source
AI summary
A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.