Semiconductor Reinforcement Plate Warpage Reduction
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Solution Overview
Problem
Conventional semiconductor devices experience warpage due to thermal expansion coefficient mismatch between the semiconductor substrate and the sealing resin, leading to mounting issues and limited multilayer interconnection structures.
Innovation Solution
A semiconductor device design featuring a reinforcement plate with matching thermal expansion coefficient to the semiconductor substrate, incorporating through-hole electrodes and multilayer interconnection structures on both sides of the plate to reduce warpage and enhance interconnection extent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sealing resin with different thermal expansion coefficient is used to seal the semiconductor chip, then the semiconductor device can be sealed and protected, but warpage occurs due to thermal expansion coefficient mismatch between the semiconductor substrate and sealing resin
Solution Approach 1:
A reinforcement plate made of silicon (same material as semiconductor substrate) is introduced as an intermediary component between the semiconductor chip and sealing resin. This plate has through-holes that accommodate the resin, creating a transition structure that mediates the thermal expansion mismatch. The silicon plate matches the semiconductor substrate's thermal expansion coefficient, while the resin-filled through-holes provide sealing, thus resolving the contradiction between sealing protection and warpage prevention.
Solution Approach 2:
The reinforcement plate structure combines silicon material (matching semiconductor substrate properties) with sealing resin (providing protection), creating a composite structure. The silicon plate with resin-filled through-holes forms a composite system that simultaneously achieves thermal expansion compatibility and sealing protection, eliminating warpage while maintaining reliability.
2Ease of manufacture
If multilayer interconnection structure is formed only on one side of the sealing resin, then the manufacturing process is simplified, but the extent of interconnection structures is limited
Solution Approach 1:
The interconnection structure is extended from a single-sided (one-dimensional) configuration to a dual-sided (two-dimensional) configuration. By forming multilayer interconnection structures on both the upper and lower sides of the reinforcement plate, the patent utilizes both surfaces for interconnection, effectively doubling the interconnection capacity and enabling more complex electrical connections without complicating the fundamental manufacturing approach.
3Area of stationary object
If the area size of the semiconductor device is reduced to match the chip size, then mounting space is optimized, but warpage control becomes more difficult due to the flexibility of smaller structures
Solution Approach 1:
The reinforcement plate acts as a counterweight or stiffening element that compensates for the flexibility inherent in smaller-area devices. By placing a rigid silicon plate (matching the chip's thermal and mechanical properties) beneath the chip and filling its through-holes with sealing resin, the structure gains enhanced mechanical stability and warpage resistance, enabling small-footprint mounting without sacrificing structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and increases the extent of multilayer interconnection structures, enabling stable mounting and improved electrical connectivity.
Implementation Method 1
the sealing resin 202 having a thermal expansion coefficient (e.g., 8 to 10 PPM) different from the thermal expansion coefficient (e.g., 3.5 PPM) of the semiconductor substrate 208
Data Source
AI summary
A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate.