Semiconductor Lead Frame Relay Inner Leads Multi-Tier Stacking
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Solution Overview
Problem
Conventional semiconductor devices face challenges in miniaturization and high-density mounting due to increased manufacturing costs and limitations in element size and circuit complexity, particularly when using depress-processed lead frames and stacked semiconductor elements on both surfaces, which lead to issues with bonding wire interference and sealing resin performance.
Innovation Solution
A semiconductor device design featuring a lead frame with outer and inner leads, where relay inner leads are used to connect electrode pads differently than outer leads, allowing for varied circuit arrangements without increasing package size, and a resin sealing structure that supports multiple tiers on a single surface without depress processing, using adhesive layers to manage wire bonding and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a depress-processed lead frame is used to increase the number of semiconductor elements, then the mounting density is improved, but the manufacturing cost increases and the element size is limited
Solution Approach 1:
The patent transitions from two-dimensional mounting on both surfaces to three-dimensional multi-tier stacking on a single surface. By utilizing vertical space through multiple tiers instead of horizontal expansion across both surfaces, the patent achieves higher mounting density without requiring depress processing, thereby reducing manufacturing costs while accommodating more semiconductor elements.
2Quantity of substance
If semiconductor elements are mounted on both surfaces of the lead frame, then the mounting density is improved, but the bonding wires may contact each other causing short circuits
Solution Approach 1:
The patent resolves the bonding wire interference issue by moving from horizontal arrangement on both surfaces to vertical arrangement in multiple tiers on a single surface. This dimensional change separates the bonding wire paths in the vertical direction, eliminating the risk of wire contact and short circuits while maintaining high mounting density through efficient use of vertical space.
3Quantity of substance
If semiconductor elements are mounted on both surfaces, then the mounting density is improved, but the filling performance of sealing resin deteriorates
Solution Approach 1:
The patent improves sealing resin filling performance by transitioning from dual-surface mounting to single-surface multi-tier stacking. This configuration eliminates the complex gaps and irregular spaces created by dual-surface mounting, providing a more uniform sealing cavity that allows complete and consistent resin filling, thereby improving manufacturing precision and reliability.
4Adaptability or versatility
If relay inner leads are added to enable different pad arrangements, then the circuit versatility is improved, but the lead frame complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the lead frame into distinct functional zones: outer leads for external connections, inner leads for direct pad connections, and relay inner leads for re-wiring functions. This segmentation allows each lead type to serve specific purposes, enabling flexible circuit arrangements while maintaining clear structural organization that prevents excessive complexity.
5Area of moving object
If the element size is increased, then the device performance is improved, but the package size increases
Solution Approach 1:
The patent resolves the size conflict by transitioning from horizontal packaging arrangement to vertical multi-tier stacking. This allows larger semiconductor elements to be mounted on a single surface without increasing package footprint, as the vertical space is utilized for additional tiers. The package size remains compact while accommodating larger elements with improved performance.
Data Source
AI summary
A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead.