Semiconductor Relay Layout for Low-Leakage High-Frequency Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor relays experience signal leakage and degradation of high-frequency characteristics due to capacitive and inductive coupling, and long input-side electrical lengths leading to resonance phenomena.
Innovation Solution
The semiconductor relay design includes a configuration where the connection conductor is disposed between the first and second MOSFETs, with the normals to the bases' principal surfaces crossing each other, reducing capacitive and inductive coupling and shortening the input-side electrical length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the input terminal is arranged in a conventional configuration, then the structure is simple, but capacitive coupling and inductive coupling occur causing signal leakage
Solution Approach 1:
The patent repositions the input terminal in a different spatial dimension relative to the light emitting element and light receiving element. Specifically, the input terminal is arranged such that it does not form a parallel planar structure with the optical components, thereby reducing the coupling area and minimizing both capacitive and inductive coupling effects that cause signal leakage.
Solution Approach 2:
The patent introduces a ground terminal as an intermediary element between the input terminal and the optical components. This ground terminal acts as a shielding structure that reduces electromagnetic coupling by providing a reference potential and blocking parasitic electric fields, thereby improving signal transmission quality without requiring complex terminal arrangements.
2Reliability
If the input terminal is made long to ensure proper connection, then connection reliability is improved, but the electrical length increases causing resonance phenomena
Solution Approach 1:
The patent changes the spatial arrangement of the input terminal by positioning it in a different plane or orientation relative to the optical components. This dimensional change reduces the effective electrical length of the terminal trace while maintaining adequate physical connection, thereby pushing the resonance frequency higher and reducing resonance phenomena in the operating frequency range.
3Ease of manufacture
If conventional terminal arrangement is used, then manufacturing is simple, but stub resonance occurs increasing insertion loss
Solution Approach 1:
The patent extracts or removes the problematic stub structure from the conventional terminal arrangement. By repositioning the input terminal and optimizing the trace routing, the patent eliminates the formation of resonant stubs that cause insertion loss at specific frequencies, while maintaining a manufacturing process that remains relatively simple and compatible with conventional PCB fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes signal leakage and enhances output-side high-frequency characteristics by reducing parasitic capacitance and inductance, thereby increasing the resonance frequency and preventing frequency band narrowing.
Implementation Method 1
a light emitting element (2) electrically connected to the first input terminal (6) and the second input terminal (7)
Implementation Method 2
a light receiving element (51) provided on a second base (10)
Implementation Method 3
capacitive coupling and inductive coupling occur due to a structure between signal input and output
Implementation Method 4
capacitive coupling and inductive coupling occur due to a structure between signal input and output
Data Source
AI summary
A semiconductor relay includes at least a housing, a first input terminal, a second input terminal, a first output terminal, a second output terminal, a light emitting element, a light receiving element, a first MOSFET, and a second MOSFET. The light emitting element is disposed on a first principal surface of a first base, and a light receiving drive element is disposed on a second principal surface of a second base. A source electrode of the light receiving drive element and the second base are connected to each other with the same potential. The second base is disposed between the first MOSFET and the second MOSFET as viewed along a first axis. The normal to the first principal surface of the first base crosses the normal to the second principal surface of the second base.