Semiconductor Device With 3D Integrated Relay Substrate
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Solution Overview
Problem
Semiconductor devices with soldered external electrodes face issues of high resistance, larger size, limited wiring flexibility, and difficulty in achieving uniform height and accurate soldering on small areas like signal pads.
Innovation Solution
A semiconductor device design featuring a substrate with semiconductor chips, an insulating plate, and conductors forming protruding portions that extend outside, connected via a through hole and resin coverage, allowing for three-dimensional wiring and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external electrodes are soldered on semiconductor chips, then current path resistance is reduced, but device size increases and wiring flexibility is limited
Solution Approach 1:
The patent transitions from two-dimensional planar wiring on the chip surface to three-dimensional wiring by extending conductors vertically through the insulating plate. The lower portion conductors connect to chip pads from below, while upper portion conductors extend above the chip, enabling spatial optimization without increasing device footprint.
Solution Approach 2:
The patent embeds lower portion conductors within the insulating plate, nesting them between the chip and the plate's lower surface. This nesting approach allows conductors to occupy internal space rather than external volume, reducing overall device size while maintaining electrical connectivity.
2Reliability
If multiple external electrodes are soldered concurrently on semiconductor chip, then connection reliability is improved, but uniform height of electrodes becomes difficult to achieve
Solution Approach 1:
The patent divides the electrode formation process into separate stages: lower portion conductors are formed and positioned first, then upper portion conductors are added separately. This segmentation allows independent control and precision adjustment of each conductor's position and height, avoiding the uniformity problems of concurrent soldering.
Solution Approach 2:
The lower portion conductors are pre-formed and positioned on the insulating plate before the upper portion conductors are added. This preliminary action establishes a stable base structure that guides subsequent electrode formation, ensuring uniform height and proper alignment.
3Strength
If external electrodes are formed with sufficient thickness for strength, then mechanical strength is guaranteed, but accurate soldering on small area signal pads becomes difficult
Solution Approach 1:
The patent applies different properties to different parts of the conductor structure. The lower portion conductors have sufficient thickness for mechanical strength, while the upper portion conductors that contact the chip can be thinner and more precisely formed. This local differentiation allows both strength and precision to be achieved in appropriate locations.
Data Source
AI summary
A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.